US-12619550-B2 - Storing a logical-to-physical mapping in NAND memory

Abstract

A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.

Inventors

• Sanjay Subbarao

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260505

Application Date

20240923

Claims (20)

1. 1 . A system comprising: a memory device comprising a first portion and a second portion, the second portion storing a first logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device; and a processing device coupled to the memory device, the processing device comprising a primary flash translation layer (FTL) and a secondary FTL, the primary FTL configured to perform operations comprising: receiving a request specifying a logical address associated with a host-initiated operation directed at the first portion of the memory device; providing a look-up request to the secondary FTL based on the request, the look-up request specifying the logical address; the secondary FTL configured to perform operations comprising: identifying, based on the first L2P table, the physical address within the first portion of the memory device that corresponds to the logical address; and providing the physical address to the primary FTL responsive to the look-up request, the primary FTL further configured to execute the host-initiated operation at the physical address within the first portion of the memory device that corresponds to the logical address specified by the request.
2. 2 . The system of claim 1 , wherein: the physical address within the first portion of the memory device is a first physical address; the operations comprise identifying a second physical address corresponding to a physical location within the second portion of the memory device, the physical location within the second portion of the memory device corresponding to a portion of the first L2P table that specifies the first physical address.
3. 3 . The system of claim 2 , wherein the operations further comprise: accessing the portion of the first L2P table from the physical location within the second portion of the memory device.
4. 4 . The system of claim 3 , further comprising a read cache comprising multiple chunks to cache portions of the first L2P table, wherein the operations further comprise adding the accessed portion of the first L2P table to the read cache based on determining an entry in a second L2P table does not point to the read cache table.
5. 5 . The system of claim 4 , wherein a size of each chunk in the multiple chunks corresponds to an indirection unit size of the second L2P table.
6. 6 . The system of claim 5 , wherein: the indirection size of the second L2P table is a first indirection unit size; the first L2P table uses a second indirection unit size.
7. 7 . The system of claim 6 , wherein the first indirection unit size is smaller than the second indirection unit size.
8. 8 . The system of claim 4 , wherein the second L2P table is stored in one of: dynamic random-access memory (DRAM) or holographic random-access memory (HRAM).
9. 9 . The system of claim 1 , wherein the operations further comprise adding a new entry to a read cache table that is logically linked to a chunk of read cache in which the portion of the first L2P table is cached, wherein the adding of the new entry to the read cache table comprises: randomly selecting an existing entry in the read cache table; and replacing the existing entry in the read cache table with the new entry.
10. 10 . The system of claim 1 , wherein the host-initiated operation comprises one of: a read operation, a write operation, or an erase operation.
11. 11 . A method comprising: receiving, at a primary flash translation layer (FTL) of a memory sub-system controller, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device, the memory device comprising the first portion and a second portion, the second portion storing a first logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device; providing, by the primary FTL, a look-up request to a secondary FTL of the memory sub-system controller based on the request, the look-up request specifying the logical address; identifying, by the secondary FTL, based on the first L2P table, the physical address within the first portion of the memory device that corresponds to the logical address; providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request; and performing, by the primary FTL, the host-initiated operation at the physical address within the first portion of the memory device that corresponds to the logical address specified by the request.
12. 12 . The method of claim 11 , wherein: the physical address within the first portion of the memory device is a first physical address; the method comprises identifying a second physical address corresponding to a physical location within the second portion of the memory device, the physical location within the second portion of the memory device corresponding to a portion of the first L2P table that specifies the first physical address.
13. 13 . The method of claim 12 , further comprising a read cache comprising multiple chunks to cache portions of the first L2P table, wherein the operations further comprise adding the portion of the first L2P table to the read cache based on determining an entry in a second L2P table does not point to the read cache table.
14. 14 . The method of claim 13 , wherein a size of each chunk in the multiple chunks corresponds to an indirection size of the second L2P table.
15. 15 . The method of claim 14 , wherein: the indirection size of the second L2P table is a first indirection unit size; the first L2P table uses a second indirection unit size.
16. 16 . The method of claim 15 , wherein the first indirection unit size is smaller than the second indirection unit size.
17. 17 . The method of claim 13 , wherein the second L2P table is stored in one of: dynamic random-access memory (DRAM) or holographic random-access memory (HRAM).
18. 18 . The method of claim 11 , further comprising adding a new entry to a read cache table that is logically linked to a chunk of read cache in which the portion of the first L2P table is cached, wherein the adding of the new entry to the read cache table comprises: randomly selecting an existing entry in the read cache table; and replacing the existing entry in the read cache table with the new entry.
19. 19 . The method of claim 11 , wherein the host-initiated operation comprises one of: a read operation, a write operation, or an erase operation.
20. 20 . A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: receiving, at a primary flash translation layer (FTL) of a memory sub-system controller, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device, the memory device comprising the first portion and second portion, the second portion storing a first logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device; providing, by the primary FTL, a look-up request to a secondary FTL of the memory sub-system controller based on the request, the look-up request specifying the logical address; identifying, by the secondary FTL, based on the first L2P table, the physical address within the first portion of the memory device that corresponds to the logical address; providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request; and performing, by the primary FTL, the host-initiated operation at the physical address within the first portion of the memory device that corresponds to the logical address specified by the request.

Description

PRIORITY APPLICATION This application is a continuation of U.S. application Ser. No. 18/223,843, filed Jul. 19, 2023, which is a continuation of U.S. application Ser. No. 17/202,983, filed Mar. 16, 2021, now issued as U.S. Pat. No. 11,755,495, all of which are incorporated herein by reference in their entirety. TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems and, more specifically, to storing and using a logical-to-physical (L2P) mapping for a memory sub-system in a NAND memory device. BACKGROUND A memory sub-system can include one or more memory devices that store data. The memory components can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 is a block diagram illustrating an example computing environment that includes a memory sub-system, in accordance with some embodiments of the present disclosure. FIGS. 2A and 2B are block diagrams illustrating an example architecture for the memory sub-system, in accordance with some embodiments of the present disclosure. FIG. 3 is a block diagram illustrating an example caching algorithm implemented by the memory sub-system, in accordance with some embodiments of the present disclosure. FIGS. 4-6 are flow diagrams illustrating an example method for utilizing a logical to physical (L2P) table stored in a dedicated portion of a NAND memory device, in accordance with some embodiments of the present disclosure. FIG. 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION Aspects of the present disclosure are directed to using and storing a logical-to-physical (L2P) map for a memory sub-system in a NAND memory device. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. Data operations can be performed by the memory sub-system. The data operations can be host-initiated operations. For example, the host system can initiate a data operation (e.g., write, read, erase, etc.) on a memory sub-system. The host system can send access requests (e.g., write command, read command) to the memory sub-system, such as to store data on a memory device at the memory sub-system and to read data from the memory device on the memory sub-system. A memory device can be a non-volatile memory device. One example of a non-volatile memory device is a negative-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1. Some memory devices, such as NAND memory devices, include an array of memory cells (e.g., flash cells) to store data. Each cell includes a transistor, and within each cell, data is stored as the threshold voltage of the transistor. More specifically, the range of threshold voltages of a transistor can be divided into multiple regions with each region corresponding to a charge level that decodes into a data value. Memory cells in these devices can be grouped as pages that can refer to a logical unit of the memory device used to store data. One type of memory cell, for example, single level cells (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell. A memory device can include one or more arrays of SLCs, MLCs, TLCs, QLCs, or any combination of such. Within the context of a memory sub-system, a physical address identifies a physical location of data in a memory device. A logical address is a virtual address that is used by the host system as a reference to access a data unit corresponding to a physical location in the memory device. The data unit may correspond to a block, a page, or a sub-page. The memory sub-system maintains a logical to physical (L2P) table (also referred to as a “data map”) to process access requests received from the host system. The L2P table includes a mapping between physical addresses and logical addresses. Traditionally, an L2P table is stored in a dynamic random-access memory (DRAM) component of the memory sub-system. NAND cell densities within memory devices are increasing at a high rate, which increases the number of physical memory locatio