US-12619551-B2 - Caching of logical-to-physical mapping information in a memory sub-system

Abstract

A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.

Inventors

• Sanjay Subbarao

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260505

Application Date

20240927

Claims (20)

1. 1 . A system comprising: a memory device; and a processing device coupled to the memory device, the processing device comprising a primary flash translation layer (FTL) and a secondary FTL, the primary FTL configured to perform operations comprising: receiving a request specifying a logical address associated with a host-initiated operation directed at a first portion of the memory device; and providing a look-up request to the secondary FTL based on the request, the look-up request specifying the logical address; the secondary FTL configured to perform operations comprising: identifying, based on a chunk in a read cache, a physical address that corresponds to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of memory device; and providing the physical address to the primary FTL responsive to the look-up request, the primary FTL being further configured to execute the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.
2. 2 . The system of claim 1 , wherein the operations further comprise determining a chunk address corresponding to the chunk in the read cache based on the logical address and a size of the chunk.
3. 3 . The system of claim 2 , wherein determining the chunk address comprises adding the logical address to a result of multiplying the size of the chunk by an entry number corresponding to an entry in a read cache table.
4. 4 . The system of claim 3 , wherein the operations comprise identifying the entry in the read cache table based on an entry in a logical to physical (L2P) table that corresponds to the logical address.
5. 5 . The system of claim 4 , wherein the size of the chunk corresponds to an indirection size of the L2P table.
6. 6 . The system of claim 4 , wherein: the L2P table is a first L2P table; and the memory device stores a second L2P table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device.
7. 7 . The system of claim 6 , wherein: the request is a first request; the logical address is a first logical address; the host-initiated operation is a first host-initiated operation; the entry is a first entry; and the operations further comprise: receiving a second request specifying a second logical address associated with a second host-initiated operation directed at the first portion of a memory device; identifying a second entry in the first L2P table that corresponds to the second logical address; accessing a portion of the second L2P table from the second portion of the memory device identified based on the second entry in the first L2P table; and adding the accessed portion of the second L2P table to the read cache based on determining the entry in the first L2P table does not point to the read cache table.
8. 8 . The system of claim 7 , wherein the operations further comprise: identifying, based on the first L2P table, a physical location within the second portion of the memory device that corresponds to the portion of a second L2P table that specifies a second physical address within the first portion of the memory device that corresponds to the second logical address; and identifying, based on the portion of the second L2P table, the second physical address within the first portion of the memory device that corresponds to the second logical address specified by the second request; and performing the second host-initiated operation at the second physical address within the first portion of the memory device.
9. 9 . The system of claim 3 , wherein the operations further comprise: adding a new entry to the read cache table corresponding to a portion of an L2P table added to the read cache.
10. 10 . The system of claim 9 , wherein adding the new entry to the read cache table comprises: randomly selecting an existing entry in the read cache table; and replacing the existing entry in the read cache table with the new entry corresponding to the portion of the L2P table added to the read cache.
11. 11 . The system of claim 1 , wherein: the memory device is a NAND memory device comprising a first portion and a second portion; the first portion comprises multiple quad-level cells (QLCs); and the second portion comprises multiple single level cells (SLCs).
12. 12 . A method comprising: receiving, by a primary flash translation layer (FTL) of a memory sub-system controller, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device; providing, by the primary FTL, a look-up request to a secondary FTL of the memory sub-system controller based on the request, the look-up request specifying the logical address; identifying, by the secondary FTL, a physical address that corresponds to the logical address specified by the request based on a chunk in a read cache, the physical address corresponding to a physical location in the first portion of the memory device; providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request; and performing, by the primary FTL, the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.
13. 13 . The method of claim 12 , comprising determining a chunk address corresponding to the chunk in the read cache based on the logical address and a size of the chunk.
14. 14 . The method of claim 13 , wherein determining the chunk address comprises adding the logical address to a result of multiplying the size of the chunk by an entry number corresponding to an entry in a read cache table.
15. 15 . The method of claim 14 , comprising identifying the entry in the read cache table based on an entry in a logical to physical (L2P) table that corresponds to the logical address.
16. 16 . The method of claim 15 , wherein the size of the chunk corresponds to an indirection size of the L2P table.
17. 17 . The method of claim 16 , wherein: the L2P table is a first L2P table; and the memory device stores a second L2P table comprising a mapping between logical addresses and physical addresses in the first portion of the memory device.
18. 18 . The method of claim 17 , wherein: the request is a first request; the logical address is a first logical address; the host-initiated operation is a first host-initiated operation; the entry is a first entry; and the method comprises: receiving a second request specifying a second logical address associated with a second host-initiated operation directed at the first portion of a memory device; identifying a second entry in the first L2P table that corresponds to the second logical address; accessing a portion of the second L2P table from the second portion of the memory device identified based on the second entry in the first L2P table; and adding the accessed portion of the second L2P table to the read cache based on determining the entry in the first L2P table does not point to the read cache table.
19. 19 . The method of claim 18 , comprising: identifying, based on the first L2P table, a physical location within the second portion of the memory device that corresponds to the portion of a second L2P table that specifies a second physical address within the first portion of the memory device that corresponds to the second logical address; and identifying, based on the portion of the second L2P table, the second physical address within the first portion of the memory device that corresponds to the second logical address specified by the second request; and performing the second host-initiated operation at the second physical address within the first portion of the memory device.
20. 20 . A computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: receiving, by a primary flash translation layer (FTL) of the processing device, a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device; providing, by the primary FTL, a look-up request to a secondary FTL of the processing device based on the request, the look-up request specifying the logical address; identifying, by the secondary FTL, based on a chunk in a read cache, a physical address that corresponds to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of the memory device; providing, by the secondary FTL, the physical address to the primary FTL responsive to the look-up request; and performing, by the primary FTL, the host-initiated operation at the physical location within the first portion of the memory device corresponding to the physical address that corresponds to the logical address specified by the request.

Description

PRIORITY APPLICATION This application is a continuation of U.S. application Ser. No. 18/225,958, filed Jul. 25, 2023, which is a continuation of U.S. application Ser. No. 17/203,017, filed Mar. 16, 2021, now issued as U.S. Pat. No. 11,734,189, all of which are incorporated herein by reference in their entirety. TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems and, more specifically, to caching logical-to-physical (L2P) mapping information for a memory sub-system. BACKGROUND A memory sub-system can include one or more memory devices that store data. The memory components can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. FIG. 1 is a block diagram illustrating an example computing environment that includes a memory sub-system, in accordance with some embodiments of the present disclosure. FIGS. 2A and 2B are block diagrams illustrating an example architecture for the memory sub-system, in accordance with some embodiments of the present disclosure. FIG. 3 is a block diagram illustrating an example caching algorithm implemented by the memory sub-system, in accordance with some embodiments of the present disclosure. FIGS. 4-6 are flow diagrams illustrating an example method for utilizing a logical to physical (L2P) table stored in a dedicated portion of a NAND memory device, in accordance with some embodiments of the present disclosure. FIG. 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION Aspects of the present disclosure are directed to caching techniques for logical-to-physical (L2P) mapping information in a memory sub-system. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. Data operations can be performed by the memory sub-system. The data operations can be host-initiated operations. For example, the host system can initiate a data operation (e.g., write, read, erase, etc.) on a memory sub-system. The host system can send access requests (e.g., write command, read command) to the memory sub-system, such as to store data on a memory device at the memory sub-system and to read data from the memory device on the memory sub-system. A memory device can be a non-volatile memory device. One example of a non-volatile memory device is a negative-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1. Some memory devices, such as NAND memory devices, include an array of memory cells (e.g., flash cells) to store data. Each cell includes a transistor, and within each cell, data is stored as the threshold voltage of the transistor. More specifically, the range of threshold voltages of a transistor can be divided into multiple regions with each region corresponding to a charge level that decodes into a data value. Memory cells in these devices can be grouped as pages that can refer to a logical unit of the memory device used to store data. One type of memory cell, for example, single level cells (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs) can store multiple bits per cell. A memory device can include one or more arrays of SLCs, MLCs, TLCs, QLCs, or any combination of such. Within the context of a memory sub-system, a physical address identifies a physical location of data in a memory device. A logical address is a virtual address that is used by the host system as a reference to access a data unit corresponding to a physical location in the memory device. The data unit may correspond to a block, a page, or a sub-page. The memory sub-system maintains a logical to physical (L2P) table (also referred to as a “data map”) to process access requests received from the host system. The L2P table includes a mapping between physical addresses and logical addresses. Traditionally, an L2P table is stored in a dynamic random-access memory (DRAM) component of the memory sub-system. NAND cell densities within memory devices are increasing at a high rate, which increases the number of physical memory locations in the device. With an incr