US-12619555-B2 - Circuit and method for interfacing with peripheral circuits

Abstract

An interface circuit is coupled to first and second peripheral circuits. A register of the interface circuit stores a state parameter. The interface circuit is configured to: receive a write or read access request originating from a processor and directed towards a destination address in the first peripheral circuit; and generate a write and/or read operation at the first and/or the second peripheral circuit, the operation and its destination being selected according to the state value and the destination address.

Inventors

• Nicolas Anquet
• Gilles Pelissier

Assignees

• STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date

20260505

Application Date

20240327

Priority Date

20230331

Claims (20)

1. 1 . An interface circuit, comprising: a first coupling to a first peripheral circuit; a second coupling to a second peripheral circuit; a register storing a state parameter; and wherein the interface circuit is configured to: receive an access request for write or read that originates from a processor, said access request including a data value and a destination address; and generate a sequence of access operations for write and/or read at the first and second peripheral circuits, the access operations being selected according to a value of the state parameter and wherein an address in one of the first and second peripheral circuits for access operation is specified by the data value of the access request and wherein an address in the other of the first and second peripheral circuits for access operation is specified by the destination address of the access request.
2. 2 . The interface circuit according to claim 1 , wherein the value of the state parameter, the data value and the destination address specify that the access operation is for writing data generated from the address in the second peripheral circuit to the address in the first peripheral circuit.
3. 3 . The interface circuit according to claim 1 , wherein the value of the state parameter, the data value and the destination address specify that the access operation is for reading data stored at the address in the first peripheral circuit and writing that data to the address in the second peripheral circuit.
4. 4 . The interface circuit according to claim 1 , wherein the access operation comprises: writing data, generated by the second peripheral circuit, to the address in the first peripheral circuit; or reading data stored at the address in the first peripheral circuit and writing the data to the address in the second peripheral circuit, wherein a nature of the access operation is selected as a function of the value of the state parameter written in the register and the destination address.
5. 5 . The interface circuit according to claim 1 , wherein the access operation comprises: writing data generated by the second peripheral circuit, at the address in the first peripheral circuit, when the access request is an access request for writing a the data value in the first peripheral circuit and when the state parameter is programmed to a first state value; and reading data stored in the first peripheral at the address and writing the data in the second peripheral circuit when the state parameter is programmed to a second state value, different from the first state value.
6. 6 . The interface circuit according to claim 1 , wherein, when the access request is an access request for writing of data, the interface circuit is further configured to select the access operation and/or the destination of the access operation according to the data value.
7. 7 . The interface circuit according to claim 1 , wherein, when the access request is an access request for the writing of one of a first data or a second data that is different from the first data, into the first peripheral circuit and when the state parameter is programmed to a first state parameter value, the generated access operation comprises writing another data value, generated by the second peripheral circuit, at the address in the first peripheral circuit.
8. 8 . The interface circuit according to claim 7 , wherein, when the state parameter is programmed to a second state parameter value different from the first state parameter value, the access operation comprises reading data from the first peripheral circuit stored at the address and writing that data value into the second peripheral circuit.
9. 9 . The interface circuit according to claim 1 , further configured, when the state parameter is programmed to a set value, to authorize access, by the processor, to each of the first and second peripheral circuits.
10. 10 . The interface circuit according to claim 9 , wherein, when the access request is an access request for writing a forbidden data value, the generated access operation comprises programming of the value of the state parameter to the set value and removal of content from at least one of the first and second peripheral circuits.
11. 11 . The interface circuit according to claim 1 , wherein the generated access operation further comprises reading from and/or writing into a third peripheral circuit coupled to the interface circuit.
12. 12 . The interface circuit according to claim 1 , further configured, in response to the access request for read or write originating from the processor, to return a default value to the processor.
13. 13 . The interface circuit according to claim 1 , wherein when the state parameter has a first value, the access request is a request for writing of data generated by the second peripheral circuit to the address in the first peripheral circuit, and wherein when the state parameter has a second value, the access request is a request for reading data from the address in the first peripheral circuit and writing the read data to the second peripheral circuit.
14. 14 . An electronic device, comprising: the interface circuit according to claim 1 ; and the first and second peripheral circuits coupled to the interface circuit; and the processor coupled to the interface circuit and configured to transmit the access request directed towards the interface circuit.
15. 15 . The device according to claim 14 , wherein the first and second peripheral circuits comprise a first cryptographic circuit and a number generator, respectively, and wherein the interface circuit is configured to, when the state parameter is programmed to a first state value, intercept an access request for writing an encryption key originating from the processor and towards the first cryptographic circuit and control the writing of another value, generated by the number generator, at the address in the first cryptographic circuit.
16. 16 . The device according to claim 15 , further comprising a second cryptographic circuit coupled to the interface circuit, and wherein the interface circuit is configured to, when the state parameter is programmed to a second state value different from the first state value, intercept an access request originating from the processor and directed toward the first cryptographic circuit and control the writing of a data value, previously stored at in the first cryptographic circuit, into the second cryptographic circuit.
17. 17 . The device according to claim 14 , further comprising a clock reset circuit configured to activate and/or deactivate the first and second peripheral circuits and wherein the interface circuit is configured to control the clock reset circuit.
18. 18 . A method, comprising: receiving, by an interface circuit, an access request for write or read originating from a processor, said access request including a data value and a destination address; and generating, by the interface circuit, a sequence of access operations for write and/or read at a the first peripheral circuit and a second peripheral circuit coupled to the interface circuit, the access operations being selected according to a value of a state parameter stored in a register of the interface circuit and wherein an address in one of the first and second peripheral circuits for access operation is specified by the data value of the access request and wherein an address in the other of the first and second peripheral circuits for access operation is specified by the destination address of the access request.
19. 19 . The method according to claim 18 , wherein the value of the state parameter, the data value and the destination address specify that the access operation is for writing data generated from the address in the second peripheral circuit to the address in the first peripheral circuit.
20. 20 . The method according to claim 18 , wherein the value of the state parameter, the data value and the destination address specify that the access operation is for reading data stored at the address in the first peripheral circuit and writing that data to the address in the second peripheral circuit.

Description

PRIORITY CLAIM This application claims the priority benefit of French Application for Patent No. 2303154, filed on Mar. 31, 2023, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law. TECHNICAL FIELD The present disclosure generally concerns circuits and methods for interfacing with peripheral circuits. BACKGROUND Certain generic processors contained in electronic devices are required to interact with peripheral circuits. In certain cases, these peripheral circuits may ensure functions linked to security, such as cryptographic operations, for example including operations of encryption, signature and/or hash value generation, etc. A problem with interactions between the generic processor and peripheral circuits is the high demand imposed to the generic processor in terms of processing of communications with the peripheral circuits. Further, the generic processor may be required to manipulate secrets of the device, such as for example encryption keys. These secrets are, for example, manipulated by the generic processor during the execution of the cryptographic operations. However, it is desirable for software, executed by the generic processor, not to have access to these secrets. There thus exists a need for a solution to improve interactions between a generic processor and peripheral circuits. SUMMARY An embodiment provides an interface circuit coupled to at least a first peripheral circuit and a second peripheral circuit, and comprising a register storing a state parameter, the interface circuit being configured to: receive a read or write access request, originating from a processor and directed towards a destination address in the first peripheral circuit; and generate a write and/or read access operation at the first and/or the second peripheral circuit, the access operation and its destination being selected according to the state value and to the destination address. According to an embodiment, when the access request is an access request for the writing of data, the interface circuit is further configured to further select the access operation and/or its destination according to the data value. According to an embodiment, when the access request is an access request for the writing of a first data value or of a second data value, different from the first data value, into the first peripheral circuit and when the state parameter is programmed to a first state value, the generated access operation comprises the writing of another data value, generated by the second peripheral circuit, at the destination address in the first peripheral circuit. According to an embodiment, when the state parameter is programmed to a second state value, different from the first state value, the access operation comprises the reading from the first peripheral circuit of a data value stored at the destination address and the writing of the data value into the second peripheral circuit. According to an embodiment, the above circuit is further configured to, when the state parameter is programmed to a set value, authorize the access operation, by the processor, to each of the first and second peripheral circuits. According to an embodiment, when the access request is an access request for writing a forbidden data value, the generated access operation comprises the programming of the value of the state parameter to the set value and the removal of the content of at least one of the first and second peripheral circuits. According to an embodiment, the generated access operation further comprises the reading from and/or the writing into a third peripheral circuit coupled to the interface circuit. According to an embodiment, the above circuit is further configured to, as a response to the read or write access request originating from the processor, return a default value to the processor. An embodiment provides an electronic device comprising: the above interface circuit; and the first and second peripheral circuits coupled to the interface circuit; and the processor coupled to the interface circuit and configured to transmit a read or write access request to a destination address in one among the first and second peripheral circuits. According to an embodiment, the first and second peripheral circuits comprise a first cryptographic circuit and a number generator, and the interface circuit is configured to, when the state parameter is programmed to a first state value, intercept an access request for the writing of an encryption key originating from the processor and towards a destination address in the first cryptographic circuit and control the writing of another value, generated by the number generator, at the destination address in the first cryptographic circuit. According to an embodiment, the circuit further comprises a second cryptographic circuit, and the interface circuit is configured to, when the state parameter is programmed to a second state value different