US-12619557-B1 - Signal processing and transmission in electronic circuits

US12619557B1US 12619557 B1US12619557 B1US 12619557B1US-12619557-B1

Abstract

An integrated circuit (IC) chip receives an input signal on a bus connecting a number of IC chips in series. The IC chip is one of the number of IC chips. The IC chip determines whether the bus is in a busy state or an idle state. If the IC chip determines that the bus is in the idle state, the IC chip blocks communication from upstream chips on the bus, and transmit data on the bus. If the IC chip determines that the bus is in the busy state, the IC chip delays transmitting the data on the bus for a delay period, and transmits its data on the bus if the bus is determined to be in the idle state upon expiry of the delay period.

Inventors

David Carlson
Shahriar Ilislamloo

Assignees

Auradine, Inc.

Dates

Publication Date: 20260505
Application Date: 20230630

Claims (20)

1 . A method, comprising: determining, by an integrated circuit (IC) chip of a plurality of IC chips that are connected in series on a bus, availability of data for transmission on the bus; in response to determining the availability of the data for transmission on the bus, accessing, by the IC chip, the bus; upon accessing the bus, determining, by the IC chip, that the bus is in an idle state; in response to determining that the bus is in the idle state: blocking, by the IC chip using a signal processing circuit in the IC chip, communication from upstream chips of the plurality of IC chips on the bus, wherein the signal processing circuit is configured to receive a blocking signal and block the communication from the upstream chips based on the blocking signal; and transmitting, by the IC chip, the data on the bus, determining, by the IC chip, availability of additional data for transmission on the bus; in response to determining the availability of additional data for transmission on the bus, accessing, by the IC chip, the bus at a second time; upon accessing the bus the second time, determining, by the IC chip, that the bus is in a busy state; in response to determining that the bus is in the busy state, delaying, by the IC chip, transmitting the additional data on the bus for a known amount of time; upon expiry of the known amount of time, accessing, by the IC chip, the bus; upon accessing the bus, determining, by the IC chip, that the bus is in an idle state; and in response to determining that the bus is in the idle state: blocking, by the IC chip, communication from upstream chips of the plurality of IC chips on the bus; and transmitting, by the IC chip, the additional data on the bus.
2 . The method of claim 1 , wherein determining, by the IC chip, that the bus is in an idle state comprises: determining, by the IC chip, that the bus has been in a first logic state for a known amount of time following accessing the bus, wherein the first logic state is a logic high state.
3 . The method of claim 1 , wherein blocking, by the IC chip, communication from upstream chips of the plurality of IC chips on the bus comprises: blocking the communication from the upstream chips for a known amount of time that is based on one of more of a size of the data, a number of chips in the plurality of IC chips, or a propagation delay for signal transmission on the bus.
4 . The method of claim 1 , wherein determining, by the IC chip, that the bus is in the busy state comprises: accessing, by the IC chip, the bus for a known amount of time; and determining, by the IC chip, that the bus is in a second logic state at one or more time instants during the known amount of time, wherein the second logic state is a logic low state.
5 . The method of claim 1 , wherein delaying, by the IC chip, transmitting the additional data on the bus comprises: determining, based on a characteristic of the IC chip, a delay period; and delaying transmitting the additional data on the bus for the determined delay period.
6 . The method of claim 5 , wherein the characteristic of the IC chip comprises a chip identification (ID) number of the IC chip.
7 . An electronic circuit, comprising: a plurality of integrated circuit (IC) chips that are series connected using a plurality of buses, wherein an IC chip of the plurality of IC chips comprises: an input terminal on a bus of the plurality of buses connected to the IC chip, wherein the input terminal is coupled to an output terminal of an upstream neighboring chip of a plurality of IC chips that is series connected to the IC chip using the bus; an output terminal on the bus, wherein the output terminal is coupled to an input terminal of a downstream neighboring chip of the plurality of IC chips that is series connected to the IC chip using the bus, wherein the plurality of IC chips comprise the IC chip, the upstream neighboring chip, and the downstream neighboring chip; a controller circuit to manage data transmission on the bus, wherein the controller circuit is configured to: determine availability of data for transmission on the bus; in response to determining the availability of the data for transmission on the bus, access the bus; upon accessing the bus, determine that the bus is in an idle state; in response to determining that the bus is in the idle state: block, using a signal processing circuit in the IC chip, communication from upstream chips of the plurality of IC chips on the bus, wherein the signal processing circuit is configured to receive a blocking signal and block the communication from the upstream chips based on the blocking signal; and transmit the data on the bus; determine availability of additional data for transmission on the bus; in response to determining the availability of additional data for transmission on the bus, access the bus at a second time; upon accessing the bus the second time, determine that the bus is in a busy state; in response to determining that the bus is in the busy state, delay transmitting the additional data on the bus for a known amount of time; upon expiry of the known amount of time, access the bus; upon accessing the bus, determine that the bus is in an idle state; and in response to determining that the bus is in the idle state: block communication from upstream chips of the plurality of IC chips on the bus; and transmit the additional data on the bus.
8 . The electronic circuit of claim 7 , wherein determining that the bus is in the idle state comprises: determining that the bus has been in a first logic state for a known amount of time following accessing the bus, wherein the first logic state is a logic high state.
9 . The electronic circuit of claim 7 , wherein blocking communication from upstream chips of the plurality of IC chips on the bus comprises: blocking the communication from the upstream chips for a known amount of time that is based on one of more of a size of the data, a number of chips in the plurality of IC chips, or a propagation delay for signal transmission on the bus.
10 . The electronic circuit of claim 7 , wherein determining that the bus is in the busy state comprises: accessing the bus for a known amount of time; and determining that the bus is in a second logic state at one or more time instants during the known amount of time, wherein the second logic state is a logic low state.
11 . The electronic circuit of claim 7 , wherein delaying transmitting the additional data on the bus comprises: determining, based on a characteristic of the IC chip, a delay period; and delaying transmitting the additional data on the bus for the determined delay period.
12 . The electronic circuit of claim 11 , wherein the characteristic of the IC chip comprises a chip identification (ID) number of the IC chip.
13 . An integrated circuit (IC) chip, comprising: an input terminal on a bus connected to the IC chip, wherein the input terminal is coupled to an output terminal of an upstream neighboring chip of a plurality of IC chips that is series connected to the IC chip using the bus; an output terminal on the bus, wherein the output terminal is coupled to an input terminal of a downstream neighboring chip of the plurality of IC chips that is series connected to the IC chip using the bus, wherein the plurality of IC chips comprise the IC chip, the upstream neighboring chip, and the downstream neighboring chip; a controller circuit to manage data transmission on the bus, wherein the controller circuit is configured to: determine availability of data for transmission on the bus; in response to determining the availability of the data for transmission on the bus, access the bus; upon accessing the bus, determine that the bus is in an idle state; in response to determining that the bus is in the idle state: block, using a signal processing signal processing circuit in the IC chip, communication from upstream chips of the plurality of IC chips on the bus, wherein the signal processing circuit is configured to receive a blocking signal and block the communication from the upstream chips based on the blocking signal; and transmit the data on the bus; determine availability of additional data for transmission on the bus; in response to determining the availability of additional data for transmission on the bus, access the bus at a second time; upon accessing the bus the second time, determine that the bus is in a busy state; in response to determining that the bus is in the busy state, delay transmitting the additional data on the bus for a known amount of time; upon expiry of the known amount of time, access the bus; upon accessing the bus, determine that the bus is in an idle state; and in response to determining that the bus is in the idle state: block communication from upstream chips of the plurality of IC chips on the bus; and transmit the additional data on the bus.
14 . The IC chip of claim 13 , wherein determining that the bus is in the idle state comprises: determining that the bus has been in a first logic state for a known amount of time following accessing the bus, wherein the first logic state is a logic high state.
15 . The IC chip of claim 13 , wherein blocking communication from upstream chips of the plurality of IC chips on the bus comprises: blocking the communication from the upstream chips for a known amount of time that is based on one of more of a size of the data, a number of chips in the plurality of IC chips, or a propagation delay for signal transmission on the bus.
16 . The IC chip of claim 13 , wherein determining that the bus is in the busy state comprises: accessing the bus for a known amount of time; and determining that the bus is in a second logic state at one or more time instants during the known amount of time, wherein the second logic state is a logic low state.
17 . The IC chip of claim 13 , wherein delaying transmitting the additional data on the bus comprises: determining, based on a characteristic of the IC chip, a delay period; and delaying transmitting the additional data on the bus for the determined delay period.
18 . The IC chip of claim 17 , wherein the characteristic of the IC chip comprises a chip identification (ID) number of the IC chip.
19 . The IC chip of claim 13 , further comprising at least one processing unit coupled to the controller circuit, the at least one processing unit configured to: generate the data based on one or more mathematical computations performed by the at least one processing unit, and forward the data to the controller circuit.
20 . The IC chip of claim 19 , wherein the mathematical computations performed by the at least one processing unit comprises cryptographic hash computations, and wherein the data generated by the at least one processing unit comprises an indication of a result of the cryptographic hash computations.

Description

TECHNICAL FIELD The following disclosure generally relates to signal processing and transmission, and more specifically, to methods, integrated circuit (IC) chips, and electronic circuits related to processing and transmitting signals with collision prevention. BACKGROUND An electronic circuit can include multiple IC chips arranged in a particular topology, e.g., in series, in parallel, or a combination of both. Each of the IC chips in the electronic circuit can communicate with its neighboring chips. SUMMARY The present disclosure describes methods, integrated circuit (IC) chips, and electronic circuits to process and transmit signals with collision prevention. An electronic circuit includes a number of IC chips connected in series using multiple buses. The IC chips are connected such that input terminals of one IC chip are connected to output terminals of an upstream neighboring IC chip, and output terminals of the IC chip are connected to input terminals of a downstream neighboring IC chip. An IC chip of the number of IC chips receives a signal indicating data for transmission on one bus of the multiple buses. In response to receiving the signal indicating the data, the IC chip accesses the bus, and determine whether the bus is in an idle state or a busy state. In response to determining that the response bus is in the idle state, the IC chip blocks communication from upstream chips on the bus, and transmit the data on the bus. If the IC chip accesses the bus and determines that the bus is in the busy state, the IC chip delays transmitting the data on the bus for a delay period. Upon expiry of the delay period, the IC chip accesses the bus, and determines whether the bus is in an idle state or a busy state. If the response bus is in the idle state, the IC chip blocks communication from upstream chips on the bus, and transmits its data on bus. As described herein, a novel communication bus architecture that employs a loop configuration is introduced. The final output of the last chip connects to the input of the first chip, forming a continuous loop. This looping arrangement offers several benefits, including increased efficiency and fault tolerance. Moreover, the looped nature of the communication channels empowers each chip within the system with the ability to discern the transmission status of other chips. Through this intelligent feature, every chip becomes aware of ongoing transmissions by its counterparts. When a chip detects that another chip is actively transmitting data, it acts prudently by deferring its own communication. This proactive approach prevents collisions, ensuring smooth and uninterrupted data flow. Furthermore, when a chip initiates its transmission, it blocks communications from the upstream chips in the loop. This deliberate blocking step safeguards against the propagation of the current transmission indefinitely within the loop. By strategically implementing blocking mechanisms, such as logical gates or time-based protocols, the chip effectively manages the flow of information and prevents any potential data repetition issues. To guarantee the integrity of the transmitted signals, an important consideration is accounting for the time of flight—the time taken for signals to propagate through the communication channels. To address this, the chips in the electronic circuit can implement appropriate blocking periods that encompass the expected time of flight. By temporarily blocking communications from the upstream chips for the calculated duration, the chips ensure that the arriving signals align with the expected timing, which preserves signal integrity and minimizes potential synchronization issues. In a general aspect, an IC chip performs a method that comprises: determining availability of data for transmission on a bus; in response to determining the availability of the data for transmission on the bus, accessing the bus; upon accessing the bus, determining that the bus is in an idle state; in response to determining that the bus is in the idle state: blocking communication from upstream chips of a plurality of IC chips on the bus; and transmitting the data on the bus. Particular implementations may include one or more of the following features. In some implementations, determining that the bus is in an idle state comprises: determining that the bus has been in a first logic state for a known amount of time following accessing the bus, wherein the first logic state is a logic high state. In some implementations, blocking communication from upstream chips of the plurality of chips on the bus comprises: blocking the communication from the upstream chips for a known amount of time that is based on one of more of a size of the data, a number of chips in the plurality of chips, or a propagation delay for signal transmission on the bus. In some implementations, the method performed by the IC chip further comprises: determining availability of additional data for transmission on the