US-12619561-B2 - Data storage system including interface device

Abstract

Data storage systems are disclosed. In some implementations, a data storage device includes a controller coupled to a plurality of memory devices to control memory operations of the plurality of memory devices, and including M communication lanes, and an interface device configured to include N communication lanes to be connected to a host device that includes N communication lanes and to the M communication lanes of the controller, wherein the interface device includes a connector configured to connect the N communication lanes of the host device to the N communication lanes of the interface device, and a selector configured to, in response to a host port type identification signal received from the host device, selectively activate M communication lanes of the interface device, out of the N communication lanes of the interface device, to transmit or receive the data to or from the M communication lanes of the controller.

Inventors

• Wenwei Wang

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260505

Application Date

20240326

Claims (20)

1. 1 . A data storage system comprising: a controller coupled to a plurality of memory devices to control memory operations of the plurality of memory devices, and including M communication lanes, wherein M is a natural number; and an interface device configured to include N communication lanes to be connected to a host device that includes N communication lanes and to the M communication lanes of the controller, wherein N is a natural number that is larger than M, wherein the interface device includes: a connector configured to connect the N communication lanes of the host device to the N communication lanes of the interface device; and a selector configured to, in response to a host port type identification signal received from the host device, selectively activate M communication lanes of the interface device, out of the N communication lanes of the interface device, to transmit or receive the data to or from the M communication lanes of the controller, wherein the connector includes one or more shared input terminals connectable to one or more shared lanes used by a plurality of host port types, and one or more dedicated input terminals connectable to one or more dedicated lanes used by a specific host port type of the plurality of host port types.
2. 2 . The system of claim 1 , wherein the selector includes one or more second switch circuits configured to receive inputs from the connector and one or more first switch circuits configured to receive inputs from at least one of the connector or the one or more second switch circuits, wherein output terminals of the one or more second switch circuits and input terminals of the one or more first switch circuits are selected in response to the host port type identification signal received from the host device.
3. 3 . The system of claim 2 , wherein the one or more first switch circuits include a multiplexer, and the one or more second switch circuits include a demultiplexer.
4. 4 . The system of claim 2 , wherein input terminals of the one or more second switch circuits are configured to receive inputs from the one or more shared lanes and input terminals of the one or more first switch circuits are configured to receive inputs from at least one of the one or more shared lanes or the one or more dedicated lanes.
5. 5 . The system of claim 4 , wherein the one or more second switch circuits configured to receive the inputs from the one or more shared lanes include a demultiplexer, and the one or more first switch circuits configured to receive the inputs from at least one of the one or more shared lanes or the one or more dedicated lanes include a multiplexer.
6. 6 . The system of claim 2 , wherein the one or more first switch circuits include first to fourth multiplexers, and the one or more second switch circuits include first and second demultiplexers.
7. 7 . The system of claim 6 , wherein the first and second demultiplexers are configured to receive inputs from the connector, the first multiplexer is configured to receive inputs from the connector, the second multiplexer is configured to receive inputs from the connector and the first demultiplexer, the third multiplexer is configured to receive inputs from the first and second demultiplexers, and the fourth multiplexer is configured to receive inputs from the connector and the second demultiplexer.
8. 8 . The system of claim 7 , wherein output terminals of the one or more demultiplexers and input terminals of the one or more multiplexers are selected in response to a host port type identification signal received from the host device.
9. 9 . The system of claim 7 , wherein the one or more shared input terminals include first and second shared input terminals, and the one or more dedicated input terminals include first to fourth dedicated input terminals, the first and second shared input terminals connectable to the first and second shared lanes used by the plurality of host port types, and the first to fourth dedicated input terminals connectable to the first to fourth dedicated lanes used by the specific host port type of the plurality of host port types.
10. 10 . The system of claim 9 , wherein input terminals of the first and second demultiplexers are configured to receive inputs from the first and second shared lanes and input terminals of the first to fourth multiplexers are configured to receive inputs from at least one of the first and second shared lanes or the first to fourth dedicated lanes.
11. 11 . A method of operating a data storage system, the method comprising: receiving data from a host device with N communication lanes through N communication lanes of an interface device of the data storage system, wherein N is a natural number; receiving a host port type identification signal from the host device; selectively activating, in response to the host port type identification signal, M communication lanes of the interface device, out of the N communication lanes of the interface device, to perform a data communication in the data storage system, wherein N is a natural number that is larger than M; and performing a data communication between the host device and a controller in the data storage system using the M activated communication lanes, wherein the interface device includes a connector that includes one or more shared input terminals connectable to one or more shared lanes used by a plurality of host port types, and one or more dedicated input terminals connectable to one or more dedicated lanes used by a specific host port type of the plurality of host port types.
12. 12 . The method of claim 11 , wherein activating the M communication lanes of interface device out of the N communication lanes of the interface device includes activating one of first and second input terminals of a first switch circuit in response to the host port type identification signal, wherein the first input terminal of the first switch circuit is coupled to a first dedicated lane dedicated to a first host port type and the second input terminal of the first switch circuit is coupled to a second dedicated lane dedicated to a second host port type.
13. 13 . The method of claim 11 , wherein activating the M communication lanes of the interface device out of the N communication lanes of the interface device includes activating one of first and second output terminals of a second switch circuit in response to the host port type identification signal, wherein an input terminal of the second switch circuit is coupled to a shared lane shared by first and second port types.
14. 14 . The method of claim 13 , wherein activating the M communication lanes of the interface device out of the N communication lanes of the interface device further includes activating one of first and second input terminals of a first switch circuit in response to the host port type identification signal, wherein the one of first and second input terminals is coupled to the activated one of the first and second output terminals of the second switch circuit.
15. 15 . The method of claim 11 , wherein activating the M communication lanes of the interface device out of the N communication lanes of the interface device includes selecting one of a plurality of input terminals of a first switch circuit and selecting one of a plurality of output terminals of a second switch circuit.
16. 16 . A data storage system, comprising: a memory device including a plurality of memory areas configured to store data; a controller coupled to the memory device and including M communication lanes, wherein M is a natural number; and an interface device including N communication lanes and configured to carry out a method, comprising: receiving data from a host device with N communication lanes through the N communication lanes of the interface device, wherein N is a natural number that is larger than M; receiving a host port type identification signal from the host device; activating, in response to the host port type identification signal, M communication lanes of the interface device, out of the N communication lanes of the interface device, to perform a data communication in the data storage system; and performing a data communication between the host device and a controller in the data storage system using the M activated communication lanes, wherein the interface device includes a connector that includes one or more shared input terminals connectable to one or more shared lanes used by a plurality of host port types, and one or more dedicated input terminals connectable to one or more dedicated lanes used by a specific host port type of the plurality of host port types.
17. 17 . The system of claim 16 , wherein activating the M communication lanes of the interface device out of the N communication lanes of the interface device includes activating one of first and second input terminals of a first switch circuit in response to the host port type identification signal, wherein the first input terminal of the first switch circuit is coupled to a first dedicated lane dedicated to a first host port type and the second input terminal of the first switch circuit is coupled to a second dedicated lane dedicated to a second host port type.
18. 18 . The system of claim 16 , wherein activating the M communication lanes of the interface device out of the N communication lanes of the interface device includes activating one of first and second output terminals of a second switch circuit in response to the host port type identification signal, wherein an input terminal of the second switch circuit is coupled to a shared lane shared by first and second port types.
19. 19 . The system of claim 18 , wherein activating the M communication lanes of the interface device out of the N communication lanes of the interface device further includes activating one of first and second input terminals of a first switch circuit in response to the host port type identification signal, wherein the one of first and second input terminals is coupled to the activated one of the first and second output terminals of the second switch circuit.
20. 20 . The system of claim 16 , wherein activating the M communication lanes of the interface device out of the N communication lanes of the interface device includes selecting one of a plurality of input terminals of a first switch circuit and selecting one of a plurality of output terminals of a second switch circuit.

Description

TECHNICAL FIELD This patent document relates to interface devices for data storage systems. BACKGROUND Data storage systems such as hard disk drives (HDDs) or solid-state drives (SSDs) are computer components or electronic systems that store data, such as the operating system, applications, and user files. Data storage systems may have different types of interfaces, which define how data is transferred between a data storage system and other devices such as host devices. SUMMARY The disclosed technology can be implemented in some embodiments to connect a data storage system with PCIe lanes of a port type that is different from the PCIe lane port type of a host device by using switch circuits and switch algorithms. In some embodiments of the disclosed technology, a data storage system may include a controller coupled to a plurality of memory devices to control memory operations of the plurality of memory devices, and including M communication lanes, and an interface device configured to include N communication lanes to be connected to a host device that includes N communication lanes and to the M communication lanes of the controller, wherein the interface device includes a connector configured to connect the N communication lanes of the host device to the N communication lanes of the interface device, and a selector configured to, in response to a host port type identification signal received from the host device, selectively activate M communication lanes of the interface device, out of the N communication lanes of the interface device, to transmit or receive the data to or from the M communication lanes of the controller. In some embodiments of the disclosed technology, a method of operating a data storage system may include receiving data from a host device with N communication lanes through N communication lanes of the data storage system, wherein N is a natural number, receiving a host port type identification signal from the host device, activating, in response to the host port type identification signal, M communication lanes of the data storage system, out of the N communication lanes of the data storage system, to perform a data communication in the data storage system, wherein N is a natural number that is larger than M, and performing a data communication between the host device and a controller in the data storage system using the M activated communication lanes. In some embodiments of the disclosed technology, a data storage system may include a memory device including a plurality of memory areas configured to store data, a controller coupled to the memory device and including M communication lanes, wherein M is a natural number, and an interface device including N communication lanes and configured to carry out a method, comprising receiving data from a host device with N communication lanes through the N communication lanes of the interface device, wherein N is a natural number that is larger than M, receiving a host port type identification signal from the host device, activating, in response to the host port type identification signal, M communication lanes of the interface device, out of the N communication lanes of the interface device, to perform a data communication in the data storage system, and performing a data communication between the host device and a controller in the data storage system using the M activated communication lanes. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example of a memory system that can be utilized for implementing some embodiments of the disclosed technology. FIG. 2 illustrates an example configuration of a host system and a data storage system in communication with the host system that can be used to implement some embodiments of the disclosed technology. FIG. 3A illustrates an example configuration of a host and a data storage system that includes an interface device based on some embodiments of the disclosed technology. FIG. 3B illustrates another example configuration of a host and a data storage system that includes a PCIe U3/U2 combination connector, a PCIe switch, and a controller. FIG. 4 is a flow diagram that illustrates an example interface algorithm based on some embodiments of the disclosed technology. DETAILED DESCRIPTION An interface is a standard that defines how data is transferred between storage devices and other devise such as a host device. Among others, PCIe (Peripheral Component Interconnect Express) interface is a high-speed interface standard that connects various internal components in a computer system. Data storage system such as solid state drives (SSDs) have been widely adopting PCIe interface to communicate with the host. In an example where PCIe includes four lanes of PCIe interfaces that are used to transmit and receive data, two types of physical connections, U.2 and U.3, may be used. Both the U.2 and U.3 may use the same two PCIe lanes commonly, but each of the U.2 and U.3 may have two dedicated PCIe lanes. As