US-12619562-B2 - Unidirectional command bus phase drift compensation by sending the command bus delay to memory controller

Abstract

A system has an unmatched communication architecture for a unidirectional command bus and compensates for drift on the command bus based on data provided on a bidirectional data bus. The memory device has an oscillator to measure drift or an amount of delay for the command bus over a time interval. The memory device can return a value over the data bus to the memory controller based on the delay measured with the oscillator. Based on receiving the value, the memory controller can adjust configuration settings for communication on the command bus.

Inventors

• James A. McCall
• Kuljit S. Bains
• Christopher P. Mozak

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20220818

Claims (20)

1. 1 . A memory device comprising: a command bus interface to connect to a unidirectional command bus to a memory controller; an oscillator to measure an amount of delay for the command bus over a time interval; and a data bus interface to connect to a bidirectional data bus to the memory controller, the data bus to pass a value to the memory controller based on the amount of delay measured by the oscillator.
2. 2 . The memory device of claim 1 , wherein the memory device is to automatically send the value to the memory controller as part of an exit from a low power mode.
3. 3 . The memory device of claim 2 , wherein the exit from the low power mode comprises a self refresh exit (SRX).
4. 4 . The memory device of claim 2 , wherein the exit from the low power mode comprises a power down exit (PDX).
5. 5 . The memory device of claim 2 , wherein the data bus is to pass the value to the memory controller at a frequency slower than a runtime data bitrate.
6. 6 . The memory device of claim 5 , wherein the data bus is to pass the value to the memory controller at a frequency of ¼ the runtime data bitrate.
7. 7 . The memory device of claim 1 , further comprising: a register to store the value.
8. 8 . The memory device of claim 7 , wherein the oscillator is to periodically measure the amount of delay and store the value in the register.
9. 9 . The memory device of claim 8 , where the oscillator is to measure the amount of delay in conjunction with an impedance calibration (ZQCal) operation.
10. 10 . The memory device of claim 7 , wherein the memory device is to receive a polling request from the memory controller for contents of the register during runtime.
11. 11 . The memory device of claim 1 , wherein the oscillator comprises a ring oscillator specific to the command bus.
12. 12 . A system comprising: a memory controller; a data bus with bidirectional links; a command bus with unidirectional links; and a memory device coupled to the memory controller via the data bus and the command bus, the memory device including: a command bus interface to connect to the command bus; a data bus interface to connect to the data bus; and an oscillator to measure an amount of delay for the command bus over a time interval; wherein the memory device is to pass a value over the data bus to the memory controller based on the amount of delay measured by the oscillator for the command bus.
13. 13 . The system of claim 12 , wherein the memory device is to automatically send the value to the memory controller as part of a self refresh exit (SRX) or a power down exit (PDX).
14. 14 . The system of claim 12 , wherein the memory device is to pass the value to the memory controller at a frequency slower than a runtime data bitrate.
15. 15 . The system of claim 12 , the memory device comprising: a register to store the value.
16. 16 . The system of claim 15 , wherein the oscillator is to periodically measure the amount of delay and store the value in the register.
17. 17 . The system of claim 12 , wherein the memory controller is configured to adjust a communication setting for the command bus in response to receiving the value from the memory device.
18. 18 . The system of claim 12 , further comprising one or more of: a multicore host processor coupled to the memory controller; a display communicatively coupled to a host processor; a network interface communicatively coupled to a host processor; or a battery to power the system.
19. 19 . A method comprising: measuring, with an oscillator of a memory device, an amount of delay for a command bus over a time interval, the command bus having unidirectional links for a memory controller to send commands to the memory device; storing a value in a register of the memory device based on the amount of delay measured with the oscillator; and sending, over a data bus, the value from the memory device to the memory controller, the data bus having bidirectional links between the memory controller and the memory device.
20. 20 . The method of claim 19 , wherein sending the value comprises automatically sending the value as part of an exit from a low power mode.

Description

FIELD Descriptions are generally related to device communication, and more particular descriptions are related to phase drift compensation for a unidirectional command bus. BACKGROUND A memory subsystem has unidirectional command and address bus (which can be referred to as the CA bus or the command bus) and a bidirectional data bus. Memory input/output (IO) is source synchronous, where the sending device sends a strobe with the signal, which the receiving device uses to sample the information signal. The information signal is the data for the data bus and the command and address information for the command bus. A matched architecture is common, where both the information signal and the strobe travel through the same impedance delay (e.g., the RC or resistive-capacitive delay), because the circuit components track common mode noise. As double data rate (DDR) memory speeds increase, there is a move away from a matched memory IO architecture to an unmatched memory IO architecture. An unmatched architecture provides significant benefits in transfer speed, but because the circuit components do not track common mode noise, there is a misalignment between the information signal and the strobe signal, which would cause incorrect sampling in the receiving device. Temperature has a significant impact on noise, which changes the tracking of the clock signal compared to the information signal. Temperature effects do not generally affect the signal and clock alignment in a matched architecture. However, an unmatched architecture requires compensation for drift effects. With a bidirectional bus, the memory device can send the drift terms back to the host to enable the host to update transmit settings prior to send data back to the memory device receiver. There is no inherent mechanism in a unidirectional bus to provide feedback to the transmitting device. Providing feedback for the unidirectional command and address bus could be accomplished with a separate sideband bus connected to the device to send updates to the host. However, a separate sideband bus would require extra pins, and can be slower than the channel itself. BRIEF DESCRIPTION OF THE DRAWINGS The following description includes discussion of figures having illustrations given by way of example of an implementation. The drawings should be understood by way of example, and not by way of limitation. As used herein, references to one or more examples are to be understood as describing a particular feature, structure, or characteristic included in at least one implementation of the invention. Phrases such as “in one example” or “in an alternative example” appearing herein provide examples of implementations of the invention, and do not necessarily all refer to the same implementation. However, they are also not necessarily mutually exclusive. FIG. 1 is a block diagram of an example of a system with a command bus oscillator. FIG. 2 is a timing diagram of an example of sending command bus drift feedback on the data bus. FIG. 3 is a block diagram of an example of a system in which a memory controller adjusts command bus I/O settings based on feedback from a command bus oscillator on the memory device. FIG. 4 is a flow diagram of an example of a process for command bus drift compensation. FIG. 5 is a block diagram of an example of a memory subsystem in which command bus drift compensation can be implemented. FIG. 6 is a block diagram of an example of a computing system in which command bus drift compensation can be implemented. FIG. 7 is a block diagram of an example of a mobile device in which command bus drift compensation can be implemented. Descriptions of certain details and implementations follow, including non-limiting descriptions of the figures, which may depict some or all examples, and well as other potential implementations. DETAILED DESCRIPTION As described herein, a system has an unmatched communication architecture for a unidirectional command bus. As referred to above, in an unmatched architecture, the components have different noise responses, which causes a delay shift or drift between the clock and the command signal. The receiving device includes an oscillator to measure the drift for the command bus. The receiving device can provide a value over a bidirectional data bus to the sending device based on the delay measured with the oscillator. Based on receiving the value, the sending device can adjust configuration settings for communication on the command bus to compensate for drift. An unmatched communication architecture can be applied to a memory system command and address (CA) bus, which is a unidirectional bus. The signal lines in the CA bus are used as unidirectional links from the memory controller to one or more memory devices, such as dynamic random access memory (DRAM) devices. The CA bus does not have a native feedback mechanism, since it is unidirectional. Instead of adding a feedback line from the memory device to the memory controller