US-12619566-B2 - Scalable configurable chip architecture

Abstract

Provided are systems and methods for a scalable configurable chip architecture. The system includes a first cluster and a second cluster multi-chip modules, and a data network coupling the first cluster to the second cluster. Each multi-chip module in the first cluster of multi-chip modules comprising a first plurality of chips coupled together by a first interconnect, each chip of the first plurality of chips configured to facilitate processing of at least one function of a first set of functions of an autonomous vehicle (AV). Each multi-chip module in the second cluster of multi-chip modules comprising a second plurality of chips coupled together by a second interconnect, each chip of the second plurality of chips configured to facilitate processing of at least one function of a second set of functions of the AV.

Inventors

• Guillaume Binet
• Shailendra Deva
• Hsin-I Li
• Olivia Leitermann

Assignees

• MOTIONAL AD LLC

Dates

Publication Date

20260505

Application Date

20230426

Claims (15)

1. 1 . A system comprising: a first cluster of multi-chip modules, each multi-chip module in the first cluster of multi-chip modules comprising a first plurality of chiplets coupled together by a first interconnect, each chiplet of the first plurality of chiplets configured to facilitate processing of at least one function of a first set of functions of an autonomous vehicle (AV); a second cluster of multi-chip modules, each multi-chip module in the second cluster of multi-chip modules comprising a second plurality of chiplets coupled together by a second interconnect, each chiplet of the second plurality of chiplets configured to facilitate processing of at least one function of a second set of functions of the AV; and a data network coupling the first cluster to the second cluster, wherein the first interconnect and the second interconnect are cache coherent fabric interconnects.
2. 2 . The system of claim 1 , comprising a central computer coupled to the data network.
3. 3 . The system of claim 1 , wherein at least one of the first set of functions or the second set of functions comprises sensor data processing.
4. 4 . The system of claim 3 , wherein the sensor data processing comprises processing a three-dimensional point cloud or video data.
5. 5 . The system of claim 1 , wherein the data network is an Ethernet network.
6. 6 . A vehicle, comprising: a central computer; a first cluster of multi-chip modules, each multi-chip module in the first cluster of multi-chip modules comprising a first plurality of chiplets coupled together by a first interconnect, each chiplet of the first plurality of chiplets configured to facilitate processing of at least one function of a first set of functions of the vehicle; a second cluster of multi-chip modules, each multi-chip module in the second cluster of multi-chip modules comprising a second plurality of chiplets coupled together by a second interconnect, each chiplets of the second plurality of chiplets configured to facilitate processing of at least one function of a second set of functions of the vehicle; and a data network coupling the first cluster and the second cluster to the central computer, wherein the first interconnect and the second interconnect are cache coherent fabric interconnects.
7. 7 . The vehicle of claim 6 , wherein the vehicle is divided into a plurality of zones, the first set of functions comprises processing sensor data from a first set of sensors located in a first zone of the vehicle, and the second set of functions comprises processing sensor data from a second set of sensors located in a second zone of the vehicle.
8. 8 . The vehicle of claim 6 , wherein at least one of the first set of functions or the second set of functions comprises sensor data processing.
9. 9 . The vehicle of claim 8 , wherein the sensor data processing comprises processing a three-dimensional point cloud or video data.
10. 10 . The vehicle of claim 6 , wherein the data network is an Ethernet network.
11. 11 . A method, comprising: identifying, with at least one processor, a first cluster of multi-chip modules, wherein each multi-chip module in the first cluster of multi-chip modules comprises a first plurality of chiplets coupled together by a first interconnect, each chiplet of the first plurality of chiplets configured to facilitate processing of at least one function of a first set of functions of an autonomous vehicle; identifying, with the at least one processor, a second cluster of multi-chip modules, wherein each multi-chip module in the second cluster of multi-chip modules comprises a second plurality of chiplets coupled together by a second interconnect, each chiplet of the second plurality of chiplets configured to facilitate processing of at least one function of a second set of functions of the autonomous vehicle; and operating, with the at least one processor, the autonomous vehicle based on the at least one function of the first set of functions and the at least one function of the second set of functions, wherein data processing associated with the at least one function of the first set of functions and the at least one function of the second set of functions is enabled by transmitting data using cache coherent interconnects.
12. 12 . The method of claim 11 , wherein the first plurality of chiplets corresponds to a first zone of the autonomous vehicle and the second plurality of chips corresponds to a second zone of the autonomous vehicle.
13. 13 . The method of claim 11 , wherein the at least one function of the first set of functions of the autonomous vehicle is a dynamic driving task.
14. 14 . The method of claim 11 , wherein the at least one function of the second set of functions of the autonomous vehicle are driver support functions of an advanced driver assistance system.
15. 15 . The method of claim 11 , wherein the at least one function of the first set of functions or the at least one function of the second set of functions comprises sensor data processing.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims the priority of U.S. Patent Application No. 63/334,969, filed on Apr. 26, 2022, entitled “Scalable Configurable Chip Architecture,” which is herein incorporated by reference in its entirety. BACKGROUND Autonomous robotic systems, such as autonomous vehicles, rely on a suite of sensors to detect static or dynamic objects in a real-time operating environment. The detection of objects is typically performed by a perception subsystem of the autonomous robotic system that includes a neural network backbone for processing large amounts of two-dimensional (2D) and/or three-dimensional (3D) sensor data in real-time, and classifying and localizing the detected objects in the operating environment. The output of the perception subsystem is used by a planning system of the autonomous robotic system to plan a route through the operating environment. Because of the large amount of sensor data to be processed in real-time, existing distributed computing architectures are not able to meet the desired performance and safety requirements required for certain autonomous robotic systems, such as autonomous vehicles BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is an example environment in which a vehicle including one or more components of an autonomous system can be implemented; FIG. 2 is a diagram of one or more systems of a vehicle including an autonomous system; FIG. 3 is a diagram of components of one or more devices and/or one or more systems of FIGS. 1 and 2; FIG. 4A is a diagram of certain components of an autonomous system; FIG. 4B is a diagram of an implementation of a neural network; FIGS. 4C and 4D are a diagram illustrating example operation of a CNN; FIG. 5 is a diagram of a vehicle that includes a scalable configurable chip architecture; FIG. 6 illustrates an example cache coherent fabric software stack, according to an embodiment; FIG. 7 is an illustration of a scalable configurable chip architecture; FIG. 8 is an illustration of a chip package with a plurality of chips; and FIG. 9 is a process for establishing a scalable configurable chip architecture for autonomous systems. DETAILED DESCRIPTION In the following description numerous specific details are set forth in order to provide a thorough understanding of the present disclosure for the purposes of explanation. It will be apparent, however, that the embodiments described by the present disclosure can be practiced without these specific details. In some instances, well-known structures and devices are illustrated in block diagram form in order to avoid unnecessarily obscuring aspects of the present disclosure. Specific arrangements or orderings of schematic elements, such as those representing systems, devices, modules, instruction blocks, data elements, and/or the like are illustrated in the drawings for ease of description. However, it will be understood by those skilled in the art that the specific ordering or arrangement of the schematic elements in the drawings is not meant to imply that a particular order or sequence of processing, or separation of processes, is required unless explicitly described as such. Further, the inclusion of a schematic element in a drawing is not meant to imply that such element is required in all embodiments or that the features represented by such element may not be included in or combined with other elements in some embodiments unless explicitly described as such. Further, where connecting elements such as solid or dashed lines or arrows are used in the drawings to illustrate a connection, relationship, or association between or among two or more other schematic elements, the absence of any such connecting elements is not meant to imply that no connection, relationship, or association can exist. In other words, some connections, relationships, or associations between elements are not illustrated in the drawings so as not to obscure the disclosure. In addition, for ease of illustration, a single connecting element can be used to represent multiple connections, relationships or associations between elements. For example, where a connecting element represents communication of signals, data, or instructions (e.g., “software instructions”), it should be understood by those skilled in the art that such element can represent one or multiple signal paths (e.g., a bus), as may be needed, to affect the communication. Although the terms first, second, third, and/or the like are used to describe various elements, these elements should not be limited by these terms. The terms first, second, third, and/or the like are used only to distinguish one element from another. For example, a first contact could be termed a second contact and, similarly, a second contact could be termed a first contact without departing from the scope of the described embodiments. The first contact and the second contact are both contacts, but they are not the same contact. The terminology used in