US-12619571-B2 - Cryptocurrency miner and device enumeration

Abstract

A cryptocurrency miner includes a serial bus, compute modules, and a controller. Each compute module includes upstream ports, downstream ports, a pass-through buffer coupling the upstream ports to the downstream ports, and a serial bus interface coupled to the serial bus via the first upstream ports and the first downstream ports. The controller controls operation of the compute modules via commands on the serial bus. The serial bus includes bus segments between respective upstream and downstream ports of the compute modules.

Inventors

• Michael Tal
• Gil Shefer
• Rony Gutierrez

Assignees

• Chain Reaction Ltd.

Dates

Publication Date

20260505

Application Date

20240528

Claims (17)

1. 1 . A cryptocurrency miner, comprising: a controller; compute modules; and a serial bus comprising bus segments that couple the compute modules to the controller; wherein a first compute module comprises upstream ports, downstream ports, a pass-through buffer that couples the upstream ports to the downstream ports, and address registers that each default to a same predefined default address; wherein the controller is configured to open a first path of one or more bus segments to the upstream ports of the first compute module and issue a plurality of first write commands to the first compute module via the opened first path; wherein each of the plurality of first write commands is directed to the predefined default address; wherein the plurality of first write commands provides a non-default address for each address register of the first compute module; and wherein the first compute module is configured to write each non-default address provided by the plurality of first write commands to a respective address register in response to the first compute module determining that the plurality of first write commands are directed to an address stored by at least one address register of the first compute module.
2. 2 . The cryptocurrency miner of claim 1 , wherein: each first write command comprises a non-default address for each a respective address register of the first compute module; and the first compute module is configured to write each non-default address of the first write command to its respective address register.
3. 3 . The cryptocurrency miner of claim 1 , wherein the non-default address provided by at least one of the plurality of first write commands is a unicast address for the first compute module.
4. 4 . A cryptocurrency miner, comprising: a controller: compute modules; and a serial bus comprising bus segments that couple the compute modules to the controller: wherein a first compute module comprises upstream ports, downstream ports, a pass-through buffer that couples the upstream ports to the downstream ports, and address registers that each default to a same predefined default address: wherein the controller is configured to open a first path of one or more bus segments to the upstream ports of the first compute module and issue a first write command to the first compute module via the opened first path; wherein the first write command is directed to the predefined default address and provides a non-default address for an address register of the first compute module; wherein the first compute module is configured to write the non-default address provided by the first write command to the address register of the first compute module in response to the first compute module determining that the first write command is directed to an address stored by at least one address register of the first compute module; wherein a second compute module comprises upstream ports, downstream ports, a pass-through buffer that couples its upstream ports to its downstream ports, and address registers that each default to the same predefined default address as the address registers of the first compute module; wherein the controller is configured to open a second path of one or more bus segments to the upstream ports of the second compute module and issue a second write command to the second compute module via the opened second path; wherein the second write command is directed to the predefined default address and provides a non-default address for an address register of the second compute module; and wherein the second compute module is configured to write the non-default address provided by the second write command to the address register of the second compute module in response to the second compute module determining that second write commands is directed to an address stored by at least one address register of the second compute module.
5. 5 . The cryptocurrency miner of claim 4 , wherein the non-default address provided by at least one of the plural of first write command is a multicast address for a subset of the compute modules.
6. 6 . The cryptocurrency miner of claim 4 , wherein the controller opens the second path after opening the first path and issuing the first write command.
7. 7 . The cryptocurrency miner of claim 4 , wherein the second path includes the opened first path and passes through the upstream ports, the pass-through buffer, and the downstream ports of the first compute module.
8. 8 . A cryptocurrency miner, comprising: a controller; and a compute boards; wherein each compute board comprises a compute board interface, compute modules, and bus segments that couple the compute modules to the controller via its respective compute board interface; wherein each compute module comprises upstream ports, downstream ports, a pass-through buffer that couples its upstream ports to its downstream ports, and address registers that each default to a same predefined default address; wherein the controller is configured to open, for each computed module, a respective path of one or more bus segments to the upstream ports of the respective compute module and issue a plurality of write commands to the respective compute module via its respective opened path; wherein the plurality of write commands issued to a respective compute module and received by the respective compute module via its respective open path provides a non-default address for each address register of the respective compute module; and wherein each compute module is configured to write the non-default addresses provided by the plurality of write commands received via its respective opened path to its respective address registers in response to the respective compute module determining that the plurality of write commands is directed to its predefined default address stored by at least one of its respective address registers.
9. 9 . The cryptocurrency miner of claim 8 , wherein: each write command of the plurality of write commands received by each compute module comprises a non-default address for a respective address register of the respective compute module; and each compute module is configured to write the non-default addresses to their respective address registers.
10. 10 . The cryptocurrency miner of claim 8 , wherein the non-default address provided by at least one of the write commands received by each compute module is a unicast address for the respective compute module.
11. 11 . The cryptocurrency miner of claim 8 , wherein the non-default address provided by at least one of the write commands received by each compute module is a multicast address.
12. 12 . A method of a cryptocurrency miner, the method comprising: opening a first path of one or more bus segments to a first compute module of the cryptocurrency miner; issuing a plurality of first write commands to the first compute module via the opened first path; and writing non-default addresses provided by the plurality of first write commands to respective first address registers of the first compute module in response to the first compute module determining that the plurality of first write commands is directed to a predefined default address of at least one of the address registers of the first compute module.
13. 13 . The method of claim 12 , comprising initializing each address register of the first compute module to the predefined default address.
14. 14 . The method of claim 12 , comprising writing a non-default address to each address register of the first compute module in response to the first compute module receiving the plurality of first write commands.
15. 15 . The method of claim 12 , wherein writing the non-default address to the first address register comprises writing a unicast address to the first address register.
16. 16 . The method of claim 12 , wherein writing the non-default address to the first address register comprises writing a multicast address to the first address register.
17. 17 . The method of claim 12 , comprising: opening a second path of one or more bus segments to a second compute module; issuing a second write command to the second compute module via the opened second path; and writing a second non-default address provided by the second write command to a second address register of the second compute module in response to the second compute module determining that the second write command is directed to the predefined default address of at least one of the address registers of the second compute module.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 17/837,810, filed Jun. 10, 2022, the disclosure of which is hereby incorporated herein by reference in its entirety. BACKGROUND Cryptocurrency is a digital asset designed to work as a medium of exchange. Individual coin ownership records are stored in a ledger or blockchain. Unlike conventional currencies, cryptocurrency does not typically exist in a physical form and is typically not issued by a central authority. A blockchain provides a continuously growing list of records, called blocks, which are linked and secured using cryptography. Each block typically contains a hash pointer as a link to a previous block, a timestamp, and transaction data. By design, blockchains are inherently resistant to modification of the data. A blockchain is typically managed by a peer-to-peer network collectively adhering to a protocol for validating new blocks. Once recorded, the data in any given block cannot be altered retroactively without the alteration of all subsequent blocks, which requires collusion of the network majority. In cryptocurrency networks, miners validate cryptocurrency transactions of a new candidate block for the blockchain via a Proof-of-Work algorithm. A side effect of validating the candidate block is the creation of newly minted cryptocurrency. The newly minted cryptocurrency as well as associated service fees are awarded to the miner that was the first miner to validate the candidate block and thus complete the Proof-of-Work algorithm. This winner-takes-all compensation scheme has created an arms race for more efficient miners. Furthermore, mining pools have developed in an attempt to lessen the risks associated with the winner-takes-all compensation scheme. Miners or members of a mining pool share their processing power and split any obtained reward among the members according to the amount of work they contributed. Limitations and disadvantages of conventional and traditional cryptocurrency mining approaches will become apparent to one of skill in the art, through comparison of such approaches with the present disclosure as set forth in the remainder of the present disclosure with reference to the drawings. BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS FIG. 1 shows a cryptocurrency network comprising miners in accordance with various aspects of the present disclosure. FIG. 2 shows a block diagram of a miner of FIG. 1. FIG. 3 shows the miner controller of FIG. 2 coupled to compute modules via a serial bus. FIG. 4 shows a pass-through buffer of a compute module from FIG. 2. FIG. 5 shows an example command format used by the miner controller of FIG. 2. FIG. 6 shows a flowchart for an example enumeration process used by the miner controller of FIG. 2. FIGS. 7A-7D depict an example device enumeration per the enumeration process of FIG. 6 FIG. 8 shows a fault-tolerant topology for coupling slave devices such as the compute modules of FIG. 2 to a master device such as the miner controller of FIG. 2. SUMMARY Cryptocurrency miners and associated methods and apparatus are substantially shown in and/or described in connection with at least one of the figures, and are set forth more completely in the claims. Advantages, aspects, and novel features of the present disclosure, as well as details of illustrated embodiments, will be more fully understood from the following description and drawings. DETAILED DESCRIPTION OF VARIOUS ASPECTS OF THE DISCLOSURE Various aspects of the present disclosure are presented by way of example. Such examples are non-limiting, and thus the scope of various aspects of the present disclosure should not necessarily be limited by any particular characteristics of the provided examples. In the following, the phrases “for example,” “e.g.,” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limitation,” “for example and not limitation,” and the like. As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. In other words, “x and/or y” means “one or both of x and y.” As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y, and z.” The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “includes,” “comprising,” “including,” “has,” “have,” “having,” and the like specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition