US-12619572-B2 - Protocol determination circuit and protocol switching circuit

US12619572B2US 12619572 B2US12619572 B2US 12619572B2US-12619572-B2

Abstract

Noise immunity of a protocol determination circuit that determines a communication protocol between circuits is improved. A protocol determination circuit includes: a sampling circuit; and a majority decision circuit. The sampling circuit performs a plurality of number of times of sampling on a protocol specifying signal, the protocol specifying signal being any one of a value indicating a first communication protocol I2C and a value indicating a second communication protocol SPI. The majority decision circuit outputs a majority decision signal, the majority decision signal indicating a communication protocol corresponding to a value sampled majority number of times in the plurality of number of times of sampling.

Inventors

Hideyuki Amaya

Assignees

MITSUBISHI ELECTRIC CORPORATION

Dates

Publication Date: 20260505
Application Date: 20220905
Priority Date: 20211206

Claims (8)

1 . A protocol determination circuit comprising: a sampling circuit that performs a plurality of number of times of sampling on a protocol specifying signal, the protocol specifying signal being any one of a first value indicating a first communication protocol and a second value indicating a second communication protocol; and a majority decision circuit that outputs a majority decision signal and receives a reset signal, the majority decision signal indicating a communication protocol corresponding to a value sampled majority number of times in the plurality of number of times of sampling, wherein the majority decision circuit determines any one of the value indicating the first communication protocol and the value indicating the second communication protocol from a value sampled in the plurality of number of times of sampling in first communication after the reset signal is cleared, and wherein the majority decision circuit determines that the protocol specifying signal is the first communication protocol when a number of the first value is larger than a number of the second value in the plurality of number of times of sampling and determines that the protocol specifying signal is the second communication protocol when a number of the second value is larger than a number of the first value in the plurality of number of times of sampling.
2 . The protocol determination circuit according to claim 1 , wherein the sampling circuit performs each of the plurality of number of times of sampling at a timing when a clock signal alternately repeating the first value and the second value at a predetermined cycle changes from the second value to the first value, the second value being larger than the first value.
3 . The protocol determination circuit according to claim 1 , wherein the first communication protocol is I2C, and the second communication protocol is SPI.
4 . A protocol switching circuit comprising: the protocol determination circuit as recited in claim 1 ; a first communication circuit that performs communication based on the first communication protocol when the majority decision signal indicates the first communication protocol; and a second communication circuit that performs communication based on the second communication protocol when the majority decision signal indicates the second communication protocol.
5 . The protocol determination circuit according to claim 3 , wherein the protocol specifying signal is a chip select signal, the chip select signal is set to: the first value in the IC2 communication; and the second value in the SPI communication.
6 . A protocol switching circuit comprising a protocol determination circuit, the protocol determination circuit comprising: a sampling circuit that performs a plurality of number of times of sampling on a protocol specifying signal, the protocol specifying signal being any one of a value indicating a first communication protocol and a value indicating a second communication protocol; and a majority decision circuit that outputs a majority decision signal, the majority decision signal indicating a communication protocol corresponding to a value sampled majority number of times in the plurality of number of times of sampling, the protocol switching circuit further comprising: a first communication circuit that performs communication based on the first communication protocol when the majority decision signal indicates the first communication protocol; a second communication circuit that performs communication based on the second communication protocol when the majority decision signal indicates the second communication protocol; an output terminal that outputs a master-in slave-out signal from a slave to a master when the majority decision signal indicates the second communication protocol; (N−1) (N is a natural number equal to or more than 2) comparators; and a slave address determination circuit, wherein the output terminal is connected to a first input terminal of each of the (N−1) comparators, a voltage that is K/N times as high as a voltage of a power supply is input to a second input terminal of a K-th (K is a natural number equal to or more than 1 and equal to or less than (N−1)) comparator included in the (N−1) comparators, outputs of the (N−1) comparators are input to the slave address determination circuit, the slave address determination circuit outputs, to the first communication circuit, a specific slave address corresponding to the outputs of the (N−1) comparators, and the first communication circuit communicates with a slave device identified by the specific slave address.
7 . The protocol switching circuit according to claim 6 , further comprising an internal bias circuit connected to the output terminal, wherein when an impedance of the master-in slave-out signal is open, the internal bias circuit outputs, to the first input terminal of each of the (N−1) comparators, a voltage that is (K+0.5)/N times as high as the voltage of the power supply.
8 . The protocol switching circuit according to claim 7 , wherein the slave address determination circuit outputs, to the (N−1) comparators and the internal bias circuit, a sampling enable signal indicating a time period for sampling the outputs of the (N−1) comparators, and performs power down control on the (N−1) comparators and the internal bias circuit after the time period ends.

Description

TECHNICAL FIELD The present disclosure relates to a protocol determination circuit that determines a communication protocol between circuits, and a protocol switching circuit including the protocol determination circuit. BACKGROUND ART A configuration that determines a communication protocol between circuits has been conventionally known. For example, Japanese Patent Laying-Open No. 63-250759 (PTL 1) discloses an integrated circuit device that switches a communication mode between an Inter-Integrated Circuit (I2C) mode and a Serial Peripheral Interface (SPI) mode. In the integrated circuit device, the I2C mode is selected in an initial state after power on reset. When a clock input signal is High at the falling (timing of switching from High to Low) of a chip select signal, the SPI mode is selected and the communication operation is performed. When communication is started without the falling of the chip select signal, the communication operation is performed in the I2C mode that is the initial state. When a data input signal rises (changes from Low to High) in the I2C mode and a stop condition in which the clock input signal is High is satisfied, or when the rising occurs in the chip select signal in the SPI mode, it is determined that a communication end condition is satisfied, and the communication mode is returned to the I2C mode that is the initial state. CITATION LIST Patent Literature PTL 1: Japanese Patent Laying-Open No. 63-250759 SUMMARY OF INVENTION Technical Problem Usually, in I2C communication, a communication mode switching process is performed based on the premise that a chip select signal does not change, and in SPI communication, a communication mode switching process is performed based on the premise that a clock signal is High at the falling of a chip select signal. Therefore, in the integrated circuit device disclosed in PTL 1, when the chip select signal changes in the I2C mode, or when the clock signal is switched to Low at the falling of the chip select signal in the SPI mode, a protocol determination process is not appropriately performed and communication may become impossible due to superimposition of noise. The present disclosure has been made to solve the above-described problem, and an object thereof is to improve noise immunity of a protocol determination circuit that determines a communication protocol between circuits. Solution to Problem A protocol determination circuit according to the present disclosure includes: a sampling circuit; and a majority decision circuit. The sampling circuit performs a plurality of number of times of sampling on a protocol specifying signal, the protocol specifying signal being any one of a value indicating a first communication protocol and a value indicating a second communication protocol. The majority decision circuit outputs a majority decision signal, the majority decision signal indicating a communication protocol corresponding to a value sampled majority number of times in the plurality of number of times of sampling. Advantageous Effects of Invention The protocol determination circuit according to the present disclosure makes it possible to improve noise immunity of the protocol determination circuit that determines a communication protocol between circuits, by using the majority decision signal based on the plurality of number of times of sampling on the protocol specifying signal. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a block diagram showing a configuration example of a protocol switching circuit according to a first embodiment. FIG. 2 is a block diagram showing a configuration example of a protocol determination circuit shown in FIG. 1. FIG. 3 is a time chart, in the first embodiment, of each signal shown in FIGS. 1 and 2, when I2C communication is selected in a chip select signal. FIG. 4 is a time chart, in the first embodiment, of each signal shown in FIGS. 1 and 2, when SPI communication is selected in the chip select signal. FIG. 5 is a time chart, in a second embodiment, of each signal shown in FIGS. 1 and 2, when I2C communication is selected in a chip select signal. FIG. 6 is a time chart, in the second embodiment, of each signal shown in FIGS. 1 and 2, when SPI communication is selected in the chip select signal. FIG. 7 is a block diagram showing a configuration example of a protocol switching circuit according to a third embodiment. FIG. 8 is a block diagram showing a configuration example of a protocol switching circuit according to a fourth embodiment. FIG. 9 is a block diagram showing a configuration example of a protocol switching circuit according to a fifth embodiment. DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings, in which the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated in principle. First Embodiment FIG. 1 is a block diagram showing a configuration