US-12619573-B2 - Systems and methods for operating a serial peripheral interface (SPI) network

Abstract

A system includes a master device and multiple slave devices connected in a daisy chain arrangement, and configured to communicate according to a serial peripheral device interface (SPI) protocol. The master device includes circuitry to clock a series of bits into respective shift registers of the multiple slave devices, including (a) first data clocked into first shift registers of a first slave device and (b) an ignore command clocked into second shift registers of a second slave device, and use a clock signal to communicate an execute instruction to the plurality of slave devices. The execute instruction causes the first slave device to write the first data from the first shift registers to a first memory of the first slave device, whereas the execute instruction causes the second slave device to execute the ignore command to preclude a data write at a second memory of the second slave device.

Inventors

• Naveen Raj
• Christian Pillonel
• Cristian Androne
• Yann Johner

Assignees

• MICROCHIP TECHNOLOGY INCORPORATED

Dates

Publication Date

20260505

Application Date

20241015

Claims (20)

1. 1 . A system, comprising: a master device; a plurality of slave devices connected to the master device in a daisy chain arrangement, the plurality of slave devices including a first slave device having a first memory and a second slave device having a second memory; wherein the master device and the plurality of slave devices are configured to communicate according to a serial peripheral device interface (SPI) protocol; wherein the master device includes circuitry to: clock a series of bits into respective shift registers of the plurality of slave devices, including (a) first data clocked into first shift registers of the first slave device and (b) an ignore command clocked into second shift registers of the second slave device; and use a clock signal to communicate an execute instruction to the plurality of slave devices; wherein the execute instruction causes the first slave device to write the first data from the first shift registers to the first memory of the first slave device; and wherein the execute instruction causes the second slave device to execute the ignore command to preclude a data write at the second memory of the second slave device.
2. 2 . The system of claim 1 , wherein the ignore command causes the second slave device to enter a no operation mode (NOP) in response to the execute instruction.
3. 3 . The system of claim 1 , wherein the ignore command comprises a reserved address for the second slave device that is executable by the second slave device as a no operation mode (NOP) command.
4. 4 . The system of claim 1 , wherein using a clock signal to communicate an execute instruction to the plurality of slave devices comprises raising a clock signal (CS) high.
5. 5 . A method, comprising: operating a network including a master device and a plurality of slave devices connected to the master device in a daisy chain arrangement, the plurality of slave devices including a first slave device having a first memory and a second slave device having a second memory; wherein the master device and the plurality of slave devices are configured to communicate according to a serial peripheral device interface (SPI) protocol; clocking, by the master device, a series of bits into respective shift registers of the plurality of slave devices, including (a) first data clocked into first shift registers of the first slave device and (b) an ignore command clocked into second shift registers of the second slave device; and controlling a clock signal, by the master device, to communicate an execute instruction to the plurality of slave devices; wherein the execute instruction causes the first slave device to write the first data from the first shift registers to the first memory of the first slave device; and wherein the execute instruction causes the second slave device to execute the ignore command to preclude a data write at the second memory of the second slave device.
6. 6 . The method of claim 5 , wherein the ignore command causes the second slave device to enter a no operation mode (NOP) in response to the execute instruction.
7. 7 . The method of claim 5 , wherein the ignore command comprises a reserved address for the second slave device that is executable by the second slave device as a no operation mode (NOP) command.
8. 8 . A system, comprising: a master device configured to communicate data with at least one slave device according to a serial peripheral device interface (SPI) protocol; a serial data in (SDI) line connected between the master device and a first slave device of the at least one slave device; a serial clock signal (SCK) line connected between the master device and each of the at least one slave device; wherein the master device includes circuitry to initiate a slave reset procedure including: sending a predefined number of clock signals over the SCK line to each of the at least one slave device; and maintaining the SDI line at a predefined level for the duration of the predefined number of clock signals; wherein receipt of the predefined number of clock signals with the SDI line maintained at the predefined level causes each respective slave device to automatically perform an internal reset.
9. 9 . The system of claim 8 , wherein: the at least one slave device comprises a plurality of slave devices connected to the master device in a daisy chain arrangement; the SCK line is connected between the master device and each of the plurality of slave devices; the master device includes circuitry to send the predefined number of clock signals over the SCK line to each of the plurality of slave devices; and each of the plurality of slave devices includes circuitry to automatically perform an internal reset of the respective slave device in response to receiving the predefined number of clock signals with the SDI line maintained at the predefined level.
10. 10 . The system of claim 9 , comprising a chip select (CS) line connected between the master device and the first slave device; wherein the master device includes circuitry to maintain the CS line at a predefined level for the duration of the predefined number of clock signals.
11. 11 . The system of claim 9 , wherein the master device includes circuitry to: receive a reset confirmation signal from via a serial data out (SDO) line connected between the last slave device and the master device; compare a timing of the receipt of the reset confirmation signal with an expected timing of receipt of the reset confirmation signal; and determine a system status based on the comparison.
12. 12 . The system of claim 11 , wherein the expected timing of receipt of the reset confirmation signal corresponds with the predefined number of clock signals.
13. 13 . The system of claim 11 , wherein the master device includes circuitry to: in response to determining, based on the comparison, the timing of the receipt of the reset confirmation signal matches the expected timing of receipt of the reset confirmation signal, initiate a restart of normal operation of the system; and in response to determining, based on the comparison, the timing of the receipt of the reset confirmation signal does not match the expected timing of receipt of the reset confirmation signal, re-initiate the slave reset procedure.
14. 14 . The system of claim 8 , wherein the at least one slave device are connected to the master device in parallel configuration or other non-daisy chain configuration.
15. 15 . A method, comprising: communicating data from a master device to at least one slave device according to a serial peripheral device interface (SPI) protocol; wherein a serial data in (SDI) line connected between the master device and a first slave device of the at least one slave device; and wherein a serial clock signal (SCK) line connected between the master device and each of the at least one slave device; initiating, by the master device, a slave reset procedure including: sending a predefined number of clock signals over the SCK line to each of the at least one slave device; and maintaining the SDI line at a predefined level for the duration of the predefined number of clock signals; wherein receipt of the predefined number of clock signals with the SDI line maintained at the predefined level causes each respective slave device to automatically perform an internal reset.
16. 16 . The method of claim 15 , wherein the at least one slave device comprises a plurality of slave devices connected to the master device in a daisy chain arrangement.
17. 17 . The method of claim 16 , comprising, maintaining, by the master device, a chip select (CS) line, connected between the master device and the first slave device, at a predefined level for the duration of the predefined number of clock signals.
18. 18 . The method of claim 15 , comprising: receiving, by the master device, a reset confirmation signal from via a serial data out (SDO) line connected between the last slave device and the master device; comparing, by the master device, a timing of the receipt of the reset confirmation signal with an expected timing of receipt of the reset confirmation signal; and determining, by the master device, a system status based on the comparison.
19. 19 . The method of claim 18 , comprising: in response to determining, based on the comparison, the timing of the receipt of the reset confirmation signal matches the expected timing of receipt of the reset confirmation signal, initiating a restart of normal system operation by the master device; and in response to determining, based on the comparison, the timing of the receipt of the reset confirmation signal does not match the expected timing of receipt of the reset confirmation signal, re-initiating the slave reset procedure by the master device.
20. 20 . The method of claim 15 , wherein the at least one slave device comprises multiple slave devices connected to the master device in a parallel configuration or other non-daisy chain configuration.

Description

RELATED APPLICATION This application claims priority to commonly owned U.S. Provisional Ser. No. 63/682,293 filed Aug. 12, 2024, the entire contents of which are hereby incorporated by reference for all purposes. TECHNICAL FIELD The present disclosure relates to systems and methods for operating a Serial Peripheral Interface (SPI) network, for example including performing target write operations and slave device reset procedures. BACKGROUND Serial Peripheral Interface (SPI) is a synchronous serial communication protocol typically used for short-distance and high-speed synchronous data transfer between embedded systems. SPI is a three or four-wire bus and SPI devices communicate in full-duplex mode with a dedicated channel for transmitting data and a separate channel for receiving data. SPI typically contains the following wires, including (a) Serial Data Out (SDO), or Master Out Slave Input (MOSI), for host/master to target/slave communication, (b) Serial Data In (SDI), or Master Input Slave Output (MISO), target/slave to host/master communication, (c) Serial Clock (SCK), and (d) Chip Select/Serial Select (CS/SS) to select which target(s)/slave(s) to communicate with. SPI utilizes separate clock and data lines to ensure synchronicity between both the host and client. The oscillating clock signal tells the receiver when to read bits on the data line. Because both data and clock signals are synchronized, there is no need to specify clock speed. SPI generally offers faster throughput speeds compared to asynchronous serial protocols and can support multiple target/client devices (with multiple Serial Selects) so that one host device can read various sensor data. A multi-slave SPI system may be arranged in (a) an independent slave configuration, wherein the slaves are connected in parallel, and wherein a separate chip select line is connected between the master and each respective slave, or (b) a cooperative slave, or daisy chain configuration, wherein the slaves are connected in series, wherein a shared chip select line is connected between the master and all slaves, and wherein the output of each slave (except the last slave in series) is transferred to the next slave in series, and the output of the last slave in series is transferred back to the master. In a conventional daisy chain SPI system, the master reads data from each slave and then writes data to each respective slave, wherein the data written to each slave is either a copy of the data read from that slave, or new data to replace the data read from that slave. Accordingly, all slaves must be updated (i.e., requiring a read of each respective device) in order to write to any slave or slaves in the chain. This may be undesirable, as writing to a single target slave (or subset of slaves) requires superfluous reads and writes for all other slaves. There is a need for improved addressing of a single slave or subset of slaves in a daisy chain SPI system, for example without needing to update all slaves when writing to a selected slave or subset of slaves. In addition, in a conventional SPI protocol (e.g., having each an independent slave or daisy chain configuration), when the system becomes stuck/locked-up, the device must be power cycled to reset the system. Such power cycle is often impractical or impossible, for example where a battery cannot be easily removed and replaced. Alternatively, a chip select (CS) signal may be used to reset the slave devices. However, in some SPI systems, the CS is used for another purpose and is not available for a system reset function. For example an SPI system having a daisy-chain configuration may use the CS for data transfer, rendering the CS unavailable for a system reset. As another example, some SPI systems (e.g. including non-daisy chain systems) may not include a CS line, for example to save a microcontroller pin for another use. There is need for improved systems and methods to recover a locked-up SPI system, for example without requiring a power cycle and/or without using a CS signal for system reset. SUMMARY The present disclosure provides systems and methods for addressing specific slave(s) in an SPI daisy chain configuration, e.g., without disturbing the other slaves in the chain. For example, such systems and methods may allow a master device to write to a target slave or slaves, without writing to other non-targeted slaves, and thus without needing to read all devices before performing the targeted write. Avoiding such reads may provide significant time savings, especially in a system including many slaves in the chain. In some examples, a system (device network) includes a master device (master) and multiple slave devices (slaves) connected to the master in a daisy chain arrangement, wherein the master and slaves are configured to communicate with each other according to SPI protocol. The master may include circuitry (e.g., executable instructions) to (a) send a series of data to the slaves, the series of