US-12619727-B2 - Hardware trojan detection using Shapley ensemble boosting

Abstract

Various embodiments of the present disclosure provide hardware trojan detection using Shapley ensemble boosting. In one example, an embodiment provides for extracting a plurality of features related to hardware trojan detection from one or more circuit samples related to one or more circuits, training one or more machine learning models based at least in part on the plurality of features, modifying the one or more machine learning models based at least in part on a set of Shapley values to generate one or more enhanced machine learning models for hardware trojan detection related to the one or more circuits, and deploying the one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits.

Inventors

• Prabhat Kumar Mishra
• ZHIXIN PAN

Assignees

• UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED

Dates

Publication Date

20260505

Application Date

20240209

Claims (20)

1. 1 . A method for providing Shapley ensemble boosting for hardware trojan detection related to circuits, the method comprising: extracting, by one or more processors, a plurality of features related to hardware trojan detection from one or more circuit samples related to one or more circuits; training, by the one or more processors, one or more machine learning models based at least in part on the plurality of features; modifying, by the one or more processors, the one or more machine learning models based at least in part on a set of Shapley values to generate one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits, comprising adjusting one or more weights for the one or more enhanced machine learning models based at least in part on a prediction probability for a next iteration of training with respect to the one or more enhanced machine learning models; and deploying, by the one or more processors, the one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits.
2. 2 . The method of claim 1 , further comprising: adjusting one or more weights for the one or more enhanced machine learning models based at least in part on a probability of features for a next iteration of training with respect to the one or more enhanced machine learning models.
3. 3 . The method of claim 1 , further comprising: adjusting one or more weights for the one or more enhanced machine learning models based at least in part on a probability of benchmarks for a next iteration of training with respect to the one or more enhanced machine learning models.
4. 4 . The method of claim 1 , wherein the one or more machine learning models are one or more decision tree models.
5. 5 . The method of claim 1 , further comprising: selecting one or more features for one or more hardware trojan detection tasks based at least in part on the set of Shapley values.
6. 6 . The method of claim 1 , further comprising: generating a contribution measurement related to a machine learning model based at least in part on the set of Shapley values to provide at least one explainable machine learning model for hardware trojan detection.
7. 7 . The method of claim 1 , wherein the one or more enhanced machine learning models comprise multiple optimized machine learning models associated with ensemble boosting as compared to the one or more machine learning models.
8. 8 . The method of claim 7 , wherein the multiple optimized machine learning models are configured for execution in parallel to reduce an amount of time for the hardware trojan detection.
9. 9 . The method of claim 1 , wherein the one or more machine learning models are configured as a set of ensemble models, and the method further comprising: identifying one or more features in a previous ensemble model from the set of ensemble models that satisfy defined criteria for Shapley value analysis; and adjusting one or more weights in a next ensemble model from the set of ensemble models based at least in part on the one or more features to mitigate a potential misprediction of the previous ensemble model.
10. 10 . An apparatus comprising at least one processor and at least one memory including program code, the at least one memory and the program code configured to, with the at least one processor, cause the apparatus to at least: extract a plurality of features related to hardware trojan detection from one or more circuit samples related to one or more circuits; train one or more machine learning models based at least in part on the plurality of features; modify the one or more machine learning models based at least in part on a set of Shapley values to generate one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits, wherein one or more weights for the one or more enhanced machine learning models are adjusted based at least in part on a prediction probability for a next iteration of training with respect to the one or more enhanced machine learning models; and deploy the one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits.
11. 11 . The apparatus of claim 10 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: adjust one or more weights for the one or more enhanced machine learning models based at least in part on a probability of features for a next iteration of training with respect to the one or more enhanced machine learning models.
12. 12 . The apparatus of claim 10 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: adjust one or more weights for the one or more enhanced machine learning models based at least in part on a probability of benchmarks for a next iteration of training with respect to the one or more enhanced machine learning models.
13. 13 . The apparatus of claim 10 , wherein the one or more machine learning models are one or more decision tree models.
14. 14 . The apparatus of claim 10 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: select one or more features for one or more hardware trojan detection tasks based at least in part on the set of Shapley values.
15. 15 . The apparatus of claim 10 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: generate a contribution measurement related to a machine learning model based at least in part on the set of Shapley values to provide at least one explainable machine learning model for hardware trojan detection.
16. 16 . The apparatus of claim 10 , wherein the one or more enhanced machine learning models comprise multiple optimized machine learning models associated with ensemble boosting as compared to the one or more machine learning models, and wherein the multiple optimized machine learning models are configured for execution in parallel to reduce an amount of time for the hardware trojan detection.
17. 17 . The apparatus of claim 10 , wherein the one or more machine learning models are configured as a set of ensemble models, and wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least: identify one or more features in a previous ensemble model from the set of ensemble models that satisfy defined criteria for Shapley value analysis; and adjust one or more weights in a next ensemble model from the set of ensemble models based at least in part on the one or more features to mitigate a potential misprediction of the previous ensemble model.
18. 18 . A non-transitory computer storage medium comprising instructions, the instructions being configured to cause one or more processors to at least perform operations configured to: extract a plurality of features related to hardware trojan detection from one or more circuit samples related to one or more circuits; train one or more machine learning models based at least in part on the plurality of features; modify the one or more machine learning models based at least in part on a set of Shapley values to generate one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits, wherein one or more weights for the one or more enhanced machine learning models are adjusted based at least in part on a prediction probability for a next iteration of training with respect to the one or more enhanced machine learning models; and deploy the one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits.
19. 19 . The non-transitory computer storage medium of claim 18 , wherein the operations are further configured to: adjust one or more weights for the one or more enhanced machine learning models based at least in part on a probability of features for a next iteration of training with respect to the one or more enhanced machine learning models.
20. 20 . The non-transitory computer storage medium of claim 18 , wherein the operations are further configured to: adjust one or more weights for the one or more enhanced machine learning models based at least in part on a probability of benchmarks for a next iteration of training with respect to the one or more enhanced machine learning models.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Appl. No. 63/484,240 filed Feb. 10, 2023, the contents of which are incorporated herein in its entirety by reference. GOVERNMENT SUPPORT This invention was made with government support under 1908131 awarded by the National Science Foundation. The government has certain rights in the invention. TECHNICAL FIELD The present application relates to the technical field of cybersecurity for integrated circuits. In particular, the invention relates to detection, or evasion thereof, of cybersecurity attacks on semiconductor manufacturing, fabrication, testing, and/or the like with respect to integrated circuits. BACKGROUND Hardware cores are commonly employed in the semiconductor industry. Furthermore, a single System on Chip (SoC) generally comprises one or more third-party semiconductor cores such as one or more hardware Intellectual Property (IP) cores. However, hardware IP cores are generally vulnerable to security concerns such as hardware trojans. A hardware trojan is a malicious modification of a target integrated circuit (IC). Additionally, a hardware trojan is typically associated with a trigger and a payload. The trigger is typically created using a combination of rare events (e.g., rare signals or rare transitions) to stay hidden during normal execution of the IC. The payload typically represents a malicious impact on the IC design, commonly resulting in information leakage or erroneous execution of the IC. Accordingly, when the trigger is activated, the payload can enable the malicious activity. As such, an IP protection technique such as, for example, a machine learning (ML) based detection, can be employed to provide IP protection. However, ML based detection of hardware-based cybersecurity attacks typically result in various technical challenges and/or limitations. SUMMARY In general, embodiments of the present invention provide methods, apparatus, systems, computing devices, computing entities, and/or the like for providing hardware trojan detection using Shapley ensemble boosting. The details of some embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. In an embodiment, a method for providing Shapley ensemble boosting for hardware trojan detection related to circuits is provided. The method provides for extracting a plurality of features related to hardware trojan detection from one or more circuit samples related to one or more circuits, training one or more machine learning models based at least in part on the plurality of features, modifying the one or more machine learning models based at least in part on a set of Shapley values and/or one or more weight adjustments to generate one or more enhanced machine learning models for hardware trojan detection related to the one or more circuits, and deploying the one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits. In another embodiment, an apparatus is provided. The apparatus comprises at least one processor and at least one memory including program code. The at least one memory and the program code is configured to, with the at least one processor, cause the apparatus to extract a plurality of features related to hardware trojan detection from one or more circuit samples related to one or more circuits, train one or more machine learning models based at least in part on the plurality of features, modify the one or more machine learning models based at least in part on a set of Shapley values and/or one or more weight adjustments to generate one or more enhanced machine learning models for hardware trojan detection related to the one or more circuits, and deploy the one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits. In yet another embodiment, a non-transitory computer storage medium comprising instructions is provided. The instructions are configured to cause one or more processors to at least perform operations configured to extract a plurality of features related to hardware trojan detection from one or more circuit samples related to one or more circuits, train one or more machine learning models based at least in part on the plurality of features, modify the one or more machine learning models based at least in part on a set of Shapley values and/or one or more weight adjustments to generate one or more enhanced machine learning models for hardware trojan detection related to the one or more circuits, and deploy the one or more enhanced machine learning models for the hardware trojan detection related to the one or more circuits. BRIEF DESCRIPTION OF THE DRAWINGS Reference will now be made to the accompanying drawings, which are