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US-12619731-B2 - Drift detection in modular hardware systems

US12619731B2US 12619731 B2US12619731 B2US 12619731B2US-12619731-B2

Abstract

Systems and methods include Information Handling Systems (IHSs) that include one or more HPMs (Host Processor Modules), each comprising one or more CPLDs (Complex Programmable Logic Devices). Each CPLD is operated through execution of firmware, and is identified by unique hardware identifiers, and is operated using configurable settings. Each of the CPLDs is configured to transmit a bitstream of the firmware to a DC-SCM while loading the firmware for execution. The DC-SCM (Data Center Secure Control Module) determines whether the signed bitstream transmitted by each of the CPLDs matches a golden firmware measurement maintained for each respective CPLD. The DC-SCM also determines whether the unique identifiers of each of the CPLDs matches a golden hardware identity measurement maintained for each respective CPLD. The DC-SCM also determines whether the configurable settings in use by each of the CPLDs matches a golden configuration settings measurement maintained for each respective CPLD.

Inventors

  • Mukund P. Khatri
  • Eugene David CHO
  • Milton Olavo Decarvalho TAVEIRA
  • Travis Gilbert

Assignees

  • DELL PRODUCTS L.P.

Dates

Publication Date
20260505
Application Date
20240131

Claims (20)

  1. 1 . An Information Handling System (IHS), comprising: a plurality of HPMs (Host Processor Modules), each comprising: one or more CPLDs (Complex Programmable Logic Devices), each operated through the execution of firmware, and each identified by one or more unique hardware identifiers, and each operated using a plurality of configurable settings, wherein each of the CPLDs is configured to transmit a bitstream of the firmware to a DC-SCM while loading the firmware for execution; and the DC-SCM (Data Center Secure Control Module) comprising: at least one processor; and at least one memory coupled to the at least one processor, wherein the at least one memory comprises program instructions stored thereon that, upon execution by the at least one processor, cause the at least one processor to: determine whether the signed bitstream transmitted by each of the CPLDs matches a golden firmware measurement maintained for each respective CPLD; determine whether the one or more unique identifiers of each of the CPLDs matches a golden hardware identity measurement maintained for each respective CPLD; and determine whether the configurable settings in use by each of the CPLDs matches a golden configuration settings measurement maintained for each respective CPLD.
  2. 2 . The IHS of claim 1 , wherein the DC-SCM further comprises a CPLD operated through the execution of firmware, and identified by one or more unique hardware identifiers, and operated using a plurality of configurable settings.
  3. 3 . The IHS of claim 1 , wherein execution of instructions by the processor of the DC-SCM causes the processor to: determine whether firmware loaded for use by the CPLD of the DC-SCM matches a golden firmware measurement maintained for this CPLD.
  4. 4 . The IHS of claim 3 , wherein execution of instructions by the processor of the DC-SCM causes the processor to: determine whether one or more unique identifiers reported by the CPLD of the DC-SCM match a golden hardware identity measurement maintained for this CPLD.
  5. 5 . The IHS of claim 4 , wherein execution of instructions by the processor of the DC-SCM causes the processor to: determine whether one or more configurable settings reported in use by the CPLD of the DC-SCM match a golden configuration settings measurement maintained for this CPLD.
  6. 6 . The IHS of claim 1 , wherein the at least one processor comprises a platform Root-of-Trust (PRoT).
  7. 7 . The IHS of claim 1 , wherein one or more of the CPLDs comprise FPGAs (Field Programmable Gate Arrays).
  8. 8 . The IHS of claim 1 , wherein the plurality of configurable settings comprise at least one of security settings and debugging settings.
  9. 9 . The IHS of claim 8 , wherein the debugging settings comprise the status of a Joint Test Action Group (JTAG) interface of a Host Processor Module to which each respective CPLD is coupled.
  10. 10 . The IHS of claim 1 , wherein each of the CPLDs is configured to halt execution of the loaded firmware until receiving notification that the signed bitstream transmitted by each respective CPLD matches the golden firmware measurement maintained for each respective CPLD.
  11. 11 . A DC-SCM (Data Center Secure Control Module) comprising: at least one processor; and at least one memory coupled to the at least one processor, wherein the at least one memory comprises program instructions stored thereon that, upon execution by the at least one processor, cause the at least one processor to: receive a bitstream of firmware that is transmitted by a CPLD of an HPM (Host Processor Module) while loading the firmware for execution; determine when the received firmware matches a golden firmware measurement maintained for the CPLD; receive one or more unique identifiers reported by the CPLD; determine when the one or more unique identifiers reported by the CPLD matches a golden hardware identity measurement for the CPLD; receive a report of configurable settings in use by the CPLD; and determine whether the configurable settings in use by the CPLD matches a golden configuration settings measurement maintained the CPLD.
  12. 12 . The DC-SCM of claim 11 , further comprising a CPLD operated through the execution of firmware, and identified by one or more unique hardware identifiers, and operated using a plurality of configurable settings.
  13. 13 . The DC-SCM of claim 11 , wherein the at least one processor comprises a platform Root-of-Trust (PRoT).
  14. 14 . The DC-SCM of claim 11 , wherein the CPLD comprises an FPGA.
  15. 15 . The DC-SCM of claim 11 , wherein the plurality of configurable settings comprise at least one of security settings and debugging settings.
  16. 16 . One or more non-transitory computer-readable storage device storing program instructions, that when executed on or across one or more processors, cause the one or more processors to: receive a bitstream of firmware that is transmitted by a CPLD of an HPM (Host Processor Module) while loading the firmware for execution; determine when the received firmware matches a golden firmware measurement maintained for the CPLD; receive one or more unique identifiers reported by the CPLD; determine when the one or more unique identifiers reported by the CPLD matches a golden hardware identity measurement for the CPLD; receive a report of configurable settings in use by the CPLD; and determine whether the configurable settings in use by the CPLD matches a golden configuration settings measurement maintained the CPLD.
  17. 17 . The computer-readable storage device of claim 16 , wherein the at least one processor comprises a platform Root-of-Trust (PRoT).
  18. 18 . The computer-readable storage device of claim 16 , wherein the CPLD comprises an FPGA.
  19. 19 . The computer-readable storage device of claim 16 , wherein the plurality of configurable settings comprise at least one of security settings and debugging settings.
  20. 20 . The computer-readable storage device of claim 19 , wherein the debugging settings comprise the status of a Joint Test Action Group (JTAG) interface of a Host Processor Module to which each respective CPLD is coupled.

Description

FIELD This disclosure relates generally to Information Handling Systems (“IHSs”), and more specifically, to systems and methods for management of IHSs. BACKGROUND As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store it. One option available to users is an Information Handling System (“IHS”). An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. Variations in IHSs allow for IHSs to be general or configured for a specific user or specific use, such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems. The Open Compute Project's (“OCP's”) Datacenter-Modular Hardware System (“DC-MHS”) sub-project is directed to interoperability between elements of datacenter, edge, and enterprise infrastructure. DC-MHS provides consistent interfaces and form factors among modular building blocks. DC-MHS standardizes a collection of form-factors and supporting ingredients to allow interoperability between different platforms. The Security Protocol and Data Model (“SPDM”) specification defines messages, data objects, and sequences for performing message exchanges between devices over a variety of transport and physical media. The description of message exchanges includes authentication and provisioning of hardware identities, measurement for firmware identities, session key exchange protocols to enable confidentiality with integrity protected data communication and other related capabilities. Datacenter, edge, and enterprise infrastructure may include various IHSs. SUMMARY In various embodiments, systems and methods include Information Handling Systems (IHSs) that may include: a plurality of HPMs (Host Processor Modules), each comprising: one or more CPLDs (Complex Programmable Logic Devices), each operated through the execution of firmware, and each identified by one or more unique hardware identifiers, and each operated using a plurality of configurable settings, wherein each of the CPLDs is configured to transmit a bitstream of the firmware to a DC-SCM while loading the firmware for execution; and the DC-SCM (Data Center Secure Control Module) comprising: at least one processor; and at least one memory coupled to the at least one processor, wherein the at least one memory comprises program instructions stored thereon that, upon execution by the at least one processor, cause the at least one processor to: determine whether the signed bitstream transmitted by each of the CPLDs matches a golden firmware measurement maintained for each respective CPLD; determine whether the one or more unique identifiers of each of the CPLDs matches a golden hardware identity measurement maintained for each respective CPLD; and determine whether the configurable settings in use by each of the CPLDs matches a golden configuration settings measurement maintained for each respective CPLD. In some embodiments, the DC-SCM further comprises a CPLD operated through the execution of firmware, and identified by one or more unique hardware identifiers, and operated using a plurality of configurable settings. In some embodiments, execution of instructions by the processor of the DC-SCM causes the processor to: determine whether firmware loaded for use by the CPLD of the DC-SCM matches a golden firmware measurement maintained for this CPLD. In some embodiments, execution of instructions by the processor of the DC-SCM causes the processor to: determine whether one or more unique identifiers reported by the CPLD of the DC-SCM match a golden hardware identity measurement maintained for this CPLD. In some embodiments, execution of instructions by the processor of the DC-SCM causes the processor to: determine whether one or more configurable settings reported in use by the CPLD of the DC-SCM match a golden configuration settings measurement maintained for this CPLD. In some embodiments, the at least one processor comprises a platform Root-of-Trust (PRoT). In some embodiments, one or more of the CPLDs comprise FPGAs. In some embodiments, the plurality of configurable settings comprise at least one of security settings and debugging settings. In some embodiments, the debugging settings comprise the status of a J