US-12619743-B2 - Non-cached data transfer

Abstract

A memory controller can operate to provide various data protection schemes without a need of a cache. A unit of data transfer between the memory controller and memory devices can correspond to a size of data corresponding to a host read and/or write command. The memory controller operating without a cache can still ensure data integrity of the memory system to be compliant with standardized requirements and/or protocols, such as trusted execution engine security protocol (TSP).

Inventors

• Marco Sforzin
• Paolo Amato

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260505

Application Date

20230628

Claims (18)

1. 1 . An apparatus, comprising: a number of memory devices configured to store a number of encrypted user data blocks (UDBs), each UDB representing a discrete unit of data transfer for a host of the apparatus and the same discrete unit of data transfer between a memory controller and the number of memory devices; wherein the memory controller is configured to, in response to receipt of a host read command to access a first UDB from the number of memory devices: perform a first error detection operation on the first UDB using first error detection information generated based on the first UDB; perform a first error correction operation on the first UDB using error correction information generated based on the first UDB; decrypt the first UDB; perform a second error detection operation on the first UDB using second error detection information generated based on the first UDB; and perform, to protect data integrity and authenticity of the first UDB, an authentication operation on the first UDB using authentication data generated based on the unencrypted first UDB.
2. 2 . The apparatus of claim 1 , wherein the memory controller is configured to, prior to performing the first error detection operation on the first UDB, cause a memory device of the number of memory devices to transfer the first UDB, the first error detection information, and the error correction information to the memory controller.
3. 3 . The apparatus of claim 2 , wherein the memory controller is configured to cause, to perform the second error detection operation, the memory device to transfer the second error detection information to the memory controller.
4. 4 . The apparatus of claim 1 , wherein the memory controller is configured to perform a second error correction operation on the first UDB using second error correction information to correct a quantity of errors more than the quantity of errors or detect errors more than the quantity of errors on a subset of the first UDB transferred from one memory die of a memory device of the number of memory devices.
5. 5 . The apparatus of claim 1 , wherein the memory controller is configured to: cause a memory device of the number of memory devices to transfer a parity data block (PDB) to the memory controller to perform the first error correction operation; and perform the first error correction operation using the PDB.
6. 6 . The apparatus of claim 5 , wherein the memory controller is configured to perform the first error detection operation independently of and subsequent to the first error correction operation.
7. 7 . The apparatus of claim 5 , wherein the memory controller is configured to: perform the first error detection operation prior to the first error correction operation; perform the first error correction operation in response to the first error detection operation indicating one or more bit-errors in the first UDB; and in response to the first error detection operation indicating no errors in the first UDB, bypass the first error correction operation.
8. 8 . An apparatus, comprising: a number of memory devices each comprising a number of memory dice; and a memory controller coupled to the number of memory devices and configured to: generate, in response to receipt of a user data block (UDB) as part of a host write command, error detection information based on an unencrypted version or an encrypted version of the UDB to perform one or more error detection operations on the UDB, wherein the UDB is a unit of data corresponding to the host write command and to transfer between the number of memory devices and the memory controller; encrypt the UDB; generate parity data based on the UDB to be paired with the UDB as a stripe and to later perform an error correction operation on the stripe using the parity data; write the UDB and the parity data to the respective number of memory dice corresponding to one or more memory devices of the number of memory devices; generate authentication data based on the unencrypted version of the UDB; and write the authentication data to the one or more memory devices along with the UDB.
9. 9 . The apparatus of claim 8 , wherein the memory controller is configured to write the UDB to a first subset of the respective number of memory dice and the parity data to a second subset of the respective number of memory dice.
10. 10 . The apparatus of claim 8 , wherein the authentication data corresponds to message authentication code (MAC) data.
11. 11 . The apparatus of claim 8 , wherein: the error detection information comprises first error detection information; and the memory controller is configured to generate, prior to the encryption of the UDB, the first error detection information based on the unencrypted UDB.
12. 12 . The apparatus of claim 8 , wherein: the error detection information comprises second error detection information; and the memory controller is configured to generate the second error detection information based on the encrypted UDB subsequent to the encryption of the UDB.
13. 13 . The apparatus of claim 8 , wherein the stripe is a unit of low-power chip kill (LPCK) access.
14. 14 . The apparatus of claim 8 , wherein the stripe is a unit of redundant array of independent disks (RAID) access.
15. 15 . The apparatus of claim 8 , wherein the memory controller is configured to encrypt the UDB using an advanced encryption standard (AES) algorithm.
16. 16 . A method, comprising: performing, responsive to a host read command to access a first UDB from a memory device of a number of memory devices, a first error detection operation on the first UDB using first error detection information generated based on cypher text of the first UDB, wherein the first UDB is a discrete unit of data transfer for a host of the apparatus and the same discrete unit of data transfer from the number of memory devices; performing a first error correction operation on the first UDB using error correction information generated based on the cypher text of the first UDB; decrypting the first UDB to convert the first UDB in cypher text form to plain text form; performing an authentication operation on the first UDB using authentication data previously generated based on the plain text of the first UDB; performing a second error detection operation on the first UDB using second error detection information generated based on the plain text of the first UDB; generating authentication data based on the unencrypted data of the first UDB; and performing an authentication operation on the first UDB using the generated authentication data.
17. 17 . The method of claim 16 , further comprising: performing the first error detection operation prior to the first error correction operation; and performing the first error correction operation responsive to the first error detection operation indicating one or more bit-errors in the first UDB.
18. 18 . The method of claim 17 , further comprising: performing a second error correction operation prior to the first error detection operation to correct a quantity of errors in the first UDB; and performing the first error correction operation to correct the one or more errors that were uncorrectable from performing the second error correction operation.

Description

PRIORITY INFORMATION This application claims the benefit of U.S. Provisional Application No. 63/357,516, filed on Jun. 30, 2022, the contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, systems, and methods related to non-cached data transfer. BACKGROUND Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others. Memory devices may be coupled to a host (e.g., a host computing device) to store data, commands, and/or instructions for use by the host while the computer or electronic system is operating. For example, data, commands, and/or instructions can be transferred between the host and the memory device(s) during operation of a computing or other electronic system. A controller may be used to manage the transfer of data, commands, and/or instructions between the host and the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional block diagram of a computing system including a memory controller in accordance with a number of embodiments of the present disclosure. FIG. 2A is a functional block diagram of a memory controller having an low-power chip kill (LPCK) encoder/decoder in accordance with a number of embodiments of the present disclosure. FIG. 2B is another functional block diagram of a memory controller having an LPCK encoder/decoder in accordance with a number of embodiments of the present disclosure. FIG. 3A is a functional block diagram of a memory controller having a redundant array of independent disks (RAID) encoder/decoder in accordance with a number of embodiments of the present disclosure. FIG. 3B is another functional block diagram of a memory controller having a RAID encoder/decoder in accordance with a number of embodiments of the present disclosure. FIG. 4A is a block diagram of memory dice corresponding to one or more LPCK channels in accordance with a number of embodiments of the present disclosure. FIG. 4B-4D schematically illustrate various examples of how data of extra bits can be spread among memory dice in accordance with a number of embodiments of the present disclosure. FIG. 5A is a block diagram of memory dice corresponding to one or more RAID channels in accordance with a number of embodiments of the present disclosure. FIG. 5B schematically illustrates various examples of how data of extra bits can be spread among memory dice in accordance with a number of embodiments of the present disclosure. FIG. 6 is a flow diagram of a method for non-cached data transfer in accordance with a number of embodiments of the present disclosure. DETAILED DESCRIPTION Systems, apparatuses, and methods related to non-cached data transfer. In embodiments of the present disclosure, a memory controller operates without utilizing a cache, which eliminates a need to have a cache memory in the memory controller. Despite that data received at the memory controller is transferred without being cached, the memory controller of the embodiments is still capable of adding authentication, data security, and/or strengthened error detection capabilities to be compliant with various requirements/protocols, such as trusted execution engine security protocol (TSP). In some embodiments, the error detection capabilities (e.g., using cyclic redundancy code (CRC)) can be provided at various levels of the memory system. In one example, the error detection capability can be provided at a cache line-level to ensure the reliability of data communicated between the memory controller and the memory devices. In another example, the error detection capability can be provided at a host access request-level (e.g., read and/or write commands) to ensure the reliability of data communicated between the memory controller and a host. In some embodiments, the authentication capabilities can be provided to the memory system using various authentication schemes, such as message authentication code (MAC), although embodiments are not so limited. MAC can detect whether there have been any undesired changes