US-12619810-B2 - Chip structure with steganographic fill shape pattern

Abstract

A disclosed chip structure includes a coded pattern of dummy fill shapes with steganographically embedded information. The coded pattern is in a specific area of the chip, is a modified instance of a known pattern, and is decodable into a binary integer based on observable differences between the coded pattern and the known pattern at corresponding locations with the patterns. The location of the specific area containing the coded pattern, the decode cipher and the binary integer can be maintained as proprietary information (e.g., by a technology company or semiconductor foundry). Chip authentication can be made by a party with the proprietary information. Alternatively, the binary integer could be a means of conveying confidential information to a party that has been provided with the decode cipher and the location of the specific area containing the coded pattern. Also disclosed are system and method embodiments for designing and manufacturing the chip.

Inventors

• Osamu S. Nakagawa

Assignees

• GLOBALFOUNDRIES U.S. INC.

Dates

Publication Date

20260505

Application Date

20230110

Claims (20)

1. 1 . A structure comprising: a chip including: a substrate; metal levels on the substrate; and patterns of fill shapes, wherein the fill shapes are within the metal levels, and wherein the patterns include at least one coded pattern with steganographically embedded information.
2. 2 . The structure of claim 1 , wherein the coded pattern includes a modified instance of a known pattern and wherein the coded pattern is decodable into a binary integer as a function of observable differences between the coded pattern and the known pattern at corresponding locations.
3. 3 . The structure of claim 2 , wherein the coded pattern is missing at least one fill shape from at least one location as compared to a corresponding location in the known pattern.
4. 4 . The structure of claim 2 , wherein the coded pattern has at least one replacement fill shape in at least one location as compared to a corresponding location in the known pattern.
5. 5 . The structure of claim 2 , wherein the coded pattern has at least one rotated fill shape in at least one location as compared to a corresponding location in the known pattern.
6. 6 . The structure of claim 2 , wherein each fill shape location in the known pattern is associated with a different bit position in the binary integer, and wherein, within the coded pattern and as compared to corresponding locations within the known pattern, unmodified and modified fill shape locations are associated with first and second data values, respectively, so the coded pattern is decodable into the binary integer.
7. 7 . The structure of claim 2 , wherein each fill shape location in a specific section of the known pattern is associated with a different bit position in the binary integer, and wherein, within the coded pattern and as compared to corresponding locations within the specific section in the known pattern, unmodified and modified fill shape locations are associated with first and second data values, respectively, so the coded pattern is decodable into the binary integer.
8. 8 . The structure of claim 1 , wherein the fill shapes in the patterns include any of: metallic fill shapes within trenches in a dielectric layer of the metal levels; and dielectric fill shapes embedded within a metallic layer of the metal levels, and wherein the fill shapes are electrically isolated and non-functional.
9. 9 . A method comprising: accessing a layout of a chip including a substrate and metal levels on the substrate; and updating the layout to include patterns of fill shapes, wherein the fill shapes are within the metal levels, and wherein the patterns of fill shapes in the updated layout include at least one coded pattern with steganographically embedded information so that chips manufactured according to the updated layout include the at least one coded pattern.
10. 10 . The method of claim 9 , wherein the updating of the layout includes: inserting the patterns into the layout; and modifying at least one of known pattern of the patterns to create the coded pattern such that the steganographically embedded information is decodable into a binary integer as a function of observable differences between the coded pattern and the known pattern at corresponding locations.
11. 11 . The method of claim 10 , wherein the modifying includes removing at least one fill shape from at least one location as compared to a corresponding location in the known pattern.
12. 12 . The method of claim 10 , wherein the modifying includes replacing at least one fill shape in at least one location as compared to a corresponding location in the known pattern.
13. 13 . The method of claim 10 , wherein the modifying includes rotating at least one fill shape in at least one location as compared to a corresponding location in the known pattern.
14. 14 . The method of claim 10 , wherein each fill shape location in the known pattern is associated with a different bit position in the binary integer, and wherein, within the coded pattern and as compared to corresponding locations within the known pattern, unmodified and modified fill shape locations are associated with first and second data values, respectively, so the coded pattern is decodable into the binary integer.
15. 15 . The method of claim 10 , wherein each fill shape location in a specific section of the known pattern is associated with a different bit position in the binary integer, and wherein, within the coded pattern and as compared to corresponding locations within the specific section in the known pattern, unmodified and modified fill shape locations are associated with first and second data values, respectively, so the coded pattern is decodable into the binary integer.
16. 16 . The method of claim 10 , wherein the fill shapes in the patterns include any of: metallic fill shapes within trenches in a dielectric layer of the metal levels; and dielectric fill shapes embedded within a metallic layer of the metal levels, and wherein the fill shapes are electrically isolated and non-functional.
17. 17 . A method comprising: inspecting a coded pattern of fill shapes in a specific area of a chip, wherein the coded pattern includes steganographically embedded information; and decoding the coded pattern into a binary integer.
18. 18 . The method of claim 17 , wherein the decoding of the pattern into the binary integer is performed using a decode cipher.
19. 19 . The method of claim 18 , further comprising determining authenticity of the chip by comparing the binary integer to an expected binary integer.
20. 20 . The method of claim 18 , further comprising receiving conveyed information through the binary integer.

Description

BACKGROUND The present disclosure relates to semiconductor chips and, more particularly, to embodiments of a semiconductor chip structure with steganographic features and to system and method embodiments for designing, manufacturing, and using chip structures with such steganographic features. Technology companies and semiconductor foundries (also referred to as semiconductor fabrication plants or fabs) are continuously trying to find ways to thwart chip counterfeiters. The influx of counterfeit chips into the tech market results in lost revenues. Additionally, because such counterfeit chips are not typically subjected to the same quality controls, they are inevitably sub-standard. Sub-standard chips can lead to poor performance or even failures under normal operating conditions and, depending upon the particular application, can also lead to product safety issues. Thus, the negative impacts of counterfeit chips can include irreparable harm to a company's profits and reputation and also to potential legal liabilities (e.g., if authentic chips are not readily distinguishable from counterfeit chips). Various chip authentication techniques have been developed in an attempt to ensure chip authenticity. Typically, these techniques require on-chip functional components (e.g., e-fuses) and electrical sensing of such components. However, these authentication techniques may not be sufficiently secure to protect against particularly good counterfeits. Additionally, the results of electrical sensing used for authentication may be considered weak evidence during litigation. SUMMARY Disclosed herein are embodiments of a chip structure. The chip structure can include a substrate. The chip structure can also include patterns of fill shapes on the substrate. These patterns of fill shapes can include at least one coded pattern of fill shapes that has steganographically embedded information. This coded pattern can, for example, be decodable into a binary integer as a function of observable differences between it and a known pattern. Also disclosed herein are associated method embodiments. One method embodiment can include accessing a layout of a chip. The layout can further be updated to include patterns of fill shapes, where the patterns of fill shapes in the updated layout include at least one coded pattern with steganographically embedded information so that chips manufactured according to the updated layout include the at least one coded pattern. Another method embodiment can include inspecting a coded pattern of fill shapes in a specific area of a chip. This coded pattern can specifically include steganographically embedded information. The method can further include, based on the results of the inspection, decoding the coded pattern into a binary integer. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which: FIG. 1 is a layout diagram illustrating disclosed embodiments of a chip structure; FIG. 2 is a layout diagram illustrating other disclosed embodiments of a chip structure; FIG. 3 is a layout diagram illustrating still other disclosed embodiments of a chip structure; FIGS. 4A-4C are flow diagrams illustrating associated method embodiments for designing, manufacturing and using the disclosed chip structure embodiments; FIG. 5 is a schematic diagram illustrating embodiments of a system for designing the disclosed chip structure embodiments; FIGS. 6 and 7 are layout diagrams illustrating design processes performed according to the flow diagram of FIG. 4A; and FIG. 8 is a schematic diagram illustrative of a hardware environment for implementing aspects of the disclosed embodiments. DETAILED DESCRIPTION As mentioned above, technology companies and semiconductor foundries are continuously trying to find ways to thwart chip counterfeiters. The influx of counterfeit chips into the tech market results in lost revenues. Additionally, because such counterfeit chips are not typically subjected to the same quality controls, they are inevitably sub-standard. Sub-standard chips can lead to poor performance or even failures under normal operating conditions and, depending upon the particular application, can also lead to product safety issues. Thus, the negative impacts of counterfeit chips can include irreparable harm to a company's profits and reputation and also to potential legal liabilities (e.g., if authentic chips are not readily distinguishable from counterfeit chips). Various chip authentication techniques have been developed in an attempt to ensure chip authenticity. Typically, these techniques require on-chip functional components (e.g., e-fuses) and electrical sensing of such components. However, these authentication techniques may not be sufficiently secure to protect against particularly good counterfeits. Additionally, the results of electrical sensing used for au