US-12619811-B2 - Signal and power integrated analog analysis system and method for full chip system

US12619811B2US 12619811 B2US12619811 B2US 12619811B2US-12619811-B2

Abstract

A simulation system and a method thereof are disclosed. In the simulation system, a system power transmission model, and analog current time-domain model and digital current time-domain model are connected to obtain power noise generated after a supply current is obtained; jitter time-domain information of each interface connection circuit model under the power noise is obtained based on transmission of a clock signal outputted from a phase lock loop, by a simulation program; next, a voltage step response of a voltage measurement point when a clock terminal of each interface connection circuit model receives an ideal signal, is simulated by the simulation program to generate a first voltage time-domain model; a system waveform is generated based on the jitter time-domain information of each interface connection circuit model under the power noise, the first voltage time-domain model and data transmission, thereby obtaining an eye diagram and time-domain jitter distribution.

Inventors

Xiao-Fang GAO

Assignees

J.W.MICROELECTRONICS TECHNOLOGY CO., LTD

Dates

Publication Date: 20260505
Application Date: 20220104

Claims (8)

1 . A simulation system, comprising: a memory module configured to store a plurality of commands; a processor configured to execute the plurality of commands stored in the memory module, to perform a simulation analysis program on a full chip system, wherein the full chip system comprises a package structure, a printed circuit board, and a system on a chip (SoC), and the simulation analysis program comprises executing the following steps: generating a plurality of signal channel models corresponding to a plurality of input/output power domains, respectively, based on design layouts of the package structure and the printed circuit board; generating a system power transmission model based on the design layouts of the package structure and the printed circuit board, and distributions of power supply nodes on a layout of the SoC; establishing a plurality of interface connection circuit models for the plurality of input/output power domains, respectively; wherein each of the plurality of interface connection circuit models comprises a transmitter, a signal channel model corresponding to the transmitter, a receiver, a current measurement point and a voltage measurement point, in each of the plurality of interface connection circuit models, two ends of the signal channel model are connected to the transmitter and the receiver, respectively, and the transmitter comprises a data input terminal, a clock terminal, and an input/output power terminal, the current measurement point is disposed on the input/output power terminal, the voltage measurement point is disposed on a connection part between the signal channel model and the receiver; generating a second current time-domain model based on a response of a first current time-domain model corresponding to each of the plurality of interface connection circuit models at the current measurement point when the data input terminal receives random data; when the data input terminal of the first current time-domain model corresponding to each of the plurality of interface connection circuit models receives the random data, comparing a current data bit and a previous data bit in the random data, to obtain an interface data change corresponding to each of the plurality of first current time-domain models; generating the second current time-domain model corresponding to each of the plurality of first current time-domain models, based on the first current time-domain model corresponding to each of the plurality of interface connection circuit models, and the current step response of the current measurement point of each of the plurality of first current time-domain models and the interface data change corresponding to each of the plurality of first current time-domain models; wherein when the current data bit is the same as the previous data bit, a current of the current measurement point of the first current time-domain model is zero; and generating a third current time-domain model based on a current change at each of the power supply nodes of a digital circuit corresponding to a digital power domain; simulating a current step response of the current measurement point in each of the plurality of interface connection circuit models, by a simulation program with integrated circuit emphasis (SPICE), to generate a first current time-domain model corresponding to the each of the plurality of interface connection circuit models; and simulating a voltage step response of the voltage measurement point when the clock terminal of each of the plurality of interface connection circuit models receives an ideal signal, by the SPICE, to generate a first voltage time-domain model corresponding to the each of the plurality of interface connection circuit models; connecting to the system power transmission model, each of the plurality of second current time-domain models and each of the plurality of third current time-domain models, to generate a complete power transmission model, and obtain a power noise generated after the complete power transmission model obtains a supply current; recording a clock signal outputted by a phase lock loop, wherein the phase lock loop is connected to each of the plurality of interface connection circuit models; simulating a sensitivity of each of the plurality of interface connection circuit models to power by the SPICE, based on transmission of the clock signal outputted from the phase lock loop, to obtain jitter time-domain information of each of the plurality of interface connection circuit models under the power noise; and generating a system waveform corresponding to each of the plurality of interface connection circuit models, based on the jitter time-domain information of each of the plurality of interface connection circuit models under the power noise, the first voltage time-domain model corresponding to each of the plurality of interface connection circuit models, and data transmission in each of the plurality of interface connection circuit models, to obtain an eye diagram and a time-domain jitter distribution corresponding to each of the plurality of interface connection circuit models.
2 . The simulation system according to claim 1 , wherein a format of each of the plurality of signal channel models is based on S parameters, and a format of the system power transmission model is based on one of the S parameters and Z parameters.
3 . The simulation system according to claim 1 , wherein the simulation analysis program comprises executing the following steps: applying a VCD file to find a data change at each of the power supply nodes in the digital circuit; applying a standard cell library to find the current step response at each of the power supply nodes in any one of standard cells, to generate a current change at each of the power supply nodes in the any one of standard cells under the data change; and obtaining the current change of each of the power supply nodes by a linear superposition method, based on the standard cells belonged to each of the power supply nodes, to generate the third current time-domain model.
4 . The simulation system according to claim 1 , wherein the processor executes the plurality of commands stored in the memory module to perform a setting program before the simulation analysis program, and the setting program comprises executing the following steps: receiving and set a capacitance value of a de-coupling capacity between the digital circuit and an input/output circuit corresponding to each of input/output power domains in the SoC, and set a preset eye diagram standard corresponding to each of the input/output circuits; wherein the processor executes the plurality of commands stored in the memory module to perform an optimization program after the simulation analysis program, and the optimization program comprises: determining whether the eye diagram corresponding to each of the input/output circuits is compliant with the preset eye diagram standard, wherein when determining that the eye diagram corresponding to one of the input/output circuits is not compliant with the preset eye diagram standard, adjusting the capacitance value of the de-coupling capacitor between the one of the input/output circuits and the digital circuit, and re-execute the simulation analysis program until determining that the eye diagram corresponding to the one of the input/output circuits is compliant with the preset eye diagram standard.
5 . A simulation method of performing a simulation analysis on a full chip system, wherein the full chip system comprises a package structure, a printed circuit board and a system on a chip (SoC), and the simulation method comprises steps of: (a): generating a signal channel model corresponding to each of a plurality of input/output power domains based on design layouts of the package structure and the printed circuit board; (b): generating a system power transmission model based on the design layouts of the package structure and the printed circuit board, and the distributions of the power supply nodes on a layout of the SoC; (c): establishing an interface connection circuit model for each of the input/output power domains, wherein each of the interface connection circuit models comprises a transmitter, the signal channel model corresponding to the transmitter, a receiver, a current measurement point and a voltage measurement point, wherein in each of the plurality of interface connection circuit models, two ends of the signal channel model are connected to the transmitter and the receiver, respectively, and the transmitter comprises a data input terminal, a clock terminal and an input/output power terminal, the current measurement point is disposed on the input/output power terminal, and the voltage measurement point is disposed on a connection part between the signal channel model and the receiver; (d): simulating a current step response of the current measurement point of each of the interface connection circuit models, by a simulation program with integrated circuit emphasis (SPICE), to generate a first current time-domain model corresponding to the each of the interface connection circuit models; (e): generating a second current time-domain model based on a response of the first current time-domain model corresponding to each of the plurality of interface connection circuit models at the current measurement point when the data input terminal receives random data; when the data input terminal of the first current time-domain model corresponding to each of the plurality of interface connection circuit models receives the random data, comparing a current data bit and a previous data bit in the random data, to obtain an interface data change corresponding to each of the plurality of first current time-domain models, wherein when the current data bit is the same as the previous data bit, a current of the current measurement point of the first current time-domain model is zero; generating the second current time-domain model corresponding to each of the plurality of first current time-domain models, based on the first current time-domain model corresponding to each of the plurality of interface connection circuit models, and the current step response of the current measurement point of each of the plurality of first current time-domain models and the interface data change corresponding to each of the plurality of first current time-domain models (f): generating a third current time-domain model based on a current change of each of the power supply nodes of a digital circuit corresponding to a digital power domain; (g): connecting the system power transmission model, each of the plurality of second current time-domain models, and each of the plurality of third current time-domain models, to generate a complete power transmission model and obtain a power noise generated by the complete power transmission model after the complete power transmission model obtains a supply current; (h): recording a clock signal outputted from a phase lock loop, wherein the phase lock loop is connected to each of the plurality of interface connection circuit models; (i): simulating a sensitivity of each of plurality of interface connection circuit models to power by the SPICE based on the transmission of the clock signal outputted by the phase lock loop, to obtain jitter time-domain information of each of the plurality of interface connection circuit models under the power noise; (j): simulating a voltage step response of the voltage measurement point of each of the plurality of interface connection circuit models when the clock terminal receives an ideal signal, by the SPICE, to generate a first voltage time-domain model; and (k): generating a system waveform corresponding to each of the interface connection circuit models based on the jitter time-domain information of each of the plurality of interface connection circuit models under the power noise, the first voltage time-domain model corresponding to each of the plurality of interface connection circuit model, and transmission of the data in each of interface connection circuit models, to further obtain an eye diagram and a time-domain jitter distribution corresponding to each of the plurality of interface connection circuit models.
6 . The simulation method according to claim 5 , wherein a format of each of the plurality of signal channel models is based on S parameters, and a format of the system power transmission model is based on one of the S parameters and Z parameters.
7 . The simulation method according to claim 5 , wherein the step (f) comprises steps of: applying a VCD file to find a data change at each of the power supply nodes in the digital circuit; applying a standard cell library to find the current step response at each of the power supply nodes in any one of standard cells, to generate a current change at each of the power supply nodes in the any one of standard cells under the data change; and obtaining the current change of each of the power supply nodes by a linear superposition method, based on the standard cells belonged to each of the power supply nodes, to generate the third current time-domain model.
8 . The simulation method according to claim 5 , wherein before the step (a), the simulation method comprises steps of: receiving and setting a capacitance value of a de-coupling capacity between an input/output circuit corresponding to each input/output power domain and the digital circuit in the SoC; and after the step (k), the simulation method comprises steps of: determining whether the eye diagram corresponding to each of the input/output circuits is compliant with the preset eye diagram standard; and when the eye diagram corresponding to the input/output circuit is not compliant with the preset eye diagram standard, adjusting the capacitance value of the de-coupling capacity between the input/output circuit and the digital circuit, and executing the step (a) to the step (k) again until the eye diagram corresponding to the input/output circuit is compliant with the preset eye diagram standard.

Description

BACKGROUND 1. Technical Field The present invention is related to a simulation system and a method, and more particularly to a simulation system integrating signal integrity and power integrity, and a method thereof. 2. Description of Related Arts In recent years, high-end applications such as the Internet of Things, handheld systems, automotive electronics, high-speed computing and AI chips have emerged, and more and more functional blocks have been integrated into System on a Chip (SoC); when the working speed of ASIC and the data transmission rate of each input and output block in the special application in the SoC are getting higher and higher, the signal integrity and power integrity more and more affect each other. The power integrity covers power supplies for an ASIC core and the input and output blocks and significantly depends on the optional mode of the SoC. Generally, the power supply for the ASIC core is also used to provide power for each of the input and output blocks, and the activity of the ASIC affects the signal quality of each of the input and output blocks through the power supply for the ASIC code. Because the data transmission rate of each input and output block becomes higher and higher and the system bandwidth is limited, the jitters in the package and the printed circuit board are amplified; therefore, the system performance also needs to consider this effect. In addition, the crosstalk effect from the package and printed circuit board is also related to the operational mode of the SoC. The conventional analysis method is to quantitatively analyze the independent performance requirements of input/output interface (that is, the input and output blocks), the package and the printed circuit board, and finally perform the integrated design of the full chip system, but it causes consumptions of a lot of unnecessary manpower and material resources and the wastage of area/power consumption. Therefore, it is necessary to develop an improved technical solution to solve the above-mentioned problems. SUMMARY An objective of the present invention is to provide a simulation system and a method thereof, to solve the conventional technology problem. In order to achieve the objective, the present invention discloses a simulation system including a memory module and a processor. The memory module is configured to store a plurality of commands. The processor is configured to execute the plurality of commands stored in the memory module, to perform a simulation analysis program on a full chip system, wherein the full chip system comprises a package structure, a printed circuit board, and a system on a chip (SoC). The simulation analysis program includes a modeling module, a simulation module, a power noise module, a storage module, a jitter module, and an analysis module. The modeling module is configured to generate a plurality of signal channel models corresponding to a plurality of input/output power domains, respectively, based on design layouts of the package structure and the printed circuit board; generate a system power transmission model based on the design layouts of the package structure and the printed circuit board, and distributions of power supply nodes on a layout of the SoC; establish a plurality of interface connection circuit models for the plurality of input/output power domains, respectively; wherein each of the plurality of interface connection circuit models comprises a transmitter, a signal channel model corresponding to the transmitter, a receiver, a current measurement point and a voltage measurement point, in each of the plurality of interface connection circuit models, two ends of the signal channel model are connected to the transmitter and the receiver, respectively, and the transmitter comprises a data input terminal, a clock terminal, and an input/output power terminal, the current measurement point is disposed on the input/output power terminal, the voltage measurement point is disposed on a connection part between the signal channel model and the receiver; generate a second current time-domain model based on a response of a first current time-domain model corresponding to each of the plurality of interface connection circuit models at the current measurement point when the data input terminal receives random data; and generate a third current time-domain model based on a current change at each of the power supply nodes of a digital circuit corresponding to a digital power domain. The simulation module is connected to the modeling module and configured to simulate a current step response of the current measurement point in each of the plurality of interface connection circuit models, by a simulation program with integrated circuit emphasis (SPICE), to generate a first current time-domain model corresponding to the each of the plurality of interface connection circuit models; and simulate a voltage step response of the voltage measurement point when the clock terminal o