US-12619850-B2 - Compensation for light-induced current in an integrated circuit

US12619850B2US 12619850 B2US12619850 B2US 12619850B2US-12619850-B2

Abstract

A circuit for compensating for the effects of light exposure is provided. The circuit includes a first circuit and a light compensation circuit. The first circuit has an output terminal for providing a first current, wherein at least a portion of the first current is a function of a first light sensitive circuit component. The compensation circuit has a current mirror and a second light sensitive circuit component. The current mirror has an input terminal coupled to receive a second current that is mirrored from the first current, and an output terminal coupled to provide a third current responsive to the second current. The second light sensitive circuit component is configured to be similar to the first light sensitive circuit component and to compensate for a light induced current provided by the first light sensitive circuit component so that the third current is provided without a light induced current component.

Inventors

Slawomir Rafal Malinowski
Egas Carvalho Henes Neto
Fabien Boitard

Assignees

NXP B.V.

Dates

Publication Date: 20260505
Application Date: 20241004
Priority Date: 20231102

Claims (18)

1 . A circuit implemented on an integrated circuit, the circuit comprising: a first circuit having a first light sensitive circuit component, and an output terminal for providing a first current, wherein at least a portion of the first current is a function of the first light sensitive circuit component; and a compensation circuit having a current mirror and a second light sensitive circuit component, the current mirror having: an input terminal coupled to receive a second current that is mirrored from the first current; a first transistor having a first current electrode and a control electrode coupled to receive the first current, and a second current electrode coupled to ground; and a second transistor having a first current electrode, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to ground; and an output terminal coupled to provide a third current in response to the second current; and the second light sensitive circuit component configured to match the first light sensitive circuit component and to compensate for a light induced current provided by the first light sensitive circuit component, thereby providing the third current without a light induced current component due to the first light sensitive circuit component.
2 . The circuit of claim 1 , wherein the first and second light sensitive components each comprise an N-well resistor.
3 . The circuit of claim 2 , wherein the N-well resistor is formed in a P-substrate, and wherein the P-substrate is grounded.
4 . The circuit of claim 1 , wherein one or both of an area and resistance value of the second light sensitive circuit component is proportional to one or both of an area and resistance value of the first light sensitive circuit component.
5 . The circuit of claim 1 , wherein the second light sensitive circuit component has a first terminal and a second terminal, and wherein both the first and second terminals are coupled to both the control electrodes of the first and second transistors.
6 . The circuit of claim 5 , further comprising: a third transistor having a first current electrode coupled to a power supply voltage, a control electrode coupled to receive a first bias voltage from the first circuit, and a second current electrode coupled to the first current electrode of the first transistor; and a fourth transistor having a first current electrode coupled to the power supply voltage, and a control electrode and a second current electrode both coupled to the first current electrode of the second transistor.
7 . The circuit of claim 6 , further comprising one or more further circuits coupled to the first current electrode and the control electrode of the fourth transistor to receive a bias voltage generated by the first circuit.
8 . The circuit of claim 1 , wherein the first circuit comprises: a third transistor having a first current electrode, a second current electrode coupled to a first terminal of the first light sensitive component, and a control electrode; a fourth transistor having a first current electrode, a second current electrode coupled to ground, a control electrode and a second current electrode both coupled to the control electrode of the third transistor; and a fifth transistor having a first current electrode coupled to receive a power supply voltage, a control electrode and a second current electrode both coupled to the first current electrode of the third transistor for providing the first current that is mirrored to form the second current.
9 . The circuit of claim 1 , wherein the first circuit is implemented in an unpackaged integrated circuit for use in a radio frequency identification tag.
10 . An unpackaged integrated circuit comprising: a first circuit having a first light sensitive N-well resistor that is exposed to light during operation of the unpackaged integrated circuit, and an output terminal for providing a first current, wherein at least a portion of the first current is a function of an exposure of the first light sensitive N-well resistor to light; and a compensation circuit having a current mirror and a second light sensitive N-well resistor, the current mirror having an input terminal coupled to receive a second current that is mirrored from the first current, and an output terminal coupled to provide a third current in response to the second current, the second light sensitive N-well resistor configured to match the first light sensitive N-well resistor and to compensate for a light induced current component provided by the first light sensitive N-well resistor from the exposure to light, wherein the third current is provided without a light generated current component.
11 . The circuit of claim 10 , wherein one or both of an area and resistance value of the light sensitive N-well resistor is proportional to one or both an area and resistance value of the first light sensitive N-well resistor.
12 . A circuit to compensate for light induced current in an unpackaged integrated circuit, the circuit comprising: a first circuit having a first light sensitive N-well resistor, and an output terminal for providing a first current, wherein at least a portion of the first current is a function of the first light sensitive N-well resistor; a compensation circuit having a current mirror and a second light sensitive N-well resistor, the current mirror having an input terminal coupled to receive a second current that is mirrored from the first current, and an output terminal coupled to provide a third current in response to the second current, the second light sensitive N-well resistor configured to match the first light sensitive N-well resistor and to compensate for a light induced current component provided by the first light sensitive N-well resistor, wherein the third current is provided without a light generated current component; and the current mirror of the compensation circuit further comprising: a first transistor having a first current electrode and a control electrode coupled to receive the first current, and a second current electrode coupled to ground; and a second transistor having a first current electrode, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to ground.
13 . The circuit of claim 12 , wherein the second light sensitive N-well resistor has a first terminal and a second terminal, and wherein both the first and second terminals are coupled to both the control electrodes of the first and second transistors.
14 . A bias circuit to compensate for light induced current in an unpackaged integrated circuit, the bias circuit comprising: a first circuit comprising: a first transistor having a first current electrode coupled to a power supply voltage, and a second current electrode and a control electrode coupled together; a second transistor having a first current electrode coupled to a power supply voltage, a second current electrode, and a control electrode coupled to both the control electrode and the second current electrode of the first transistor, and a second current electrode; and a third transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode, and a second current electrode; a fourth transistor having a first current electrode and a control electrode coupled to both the second current electrode of the second transistor and to the control electrode of the third transistor, and a second current electrode coupled to a ground terminal; a light sensitive component having a first terminal coupled to the second current electrode of the third transistor, and a second terminal coupled to ground; a compensation circuit comprising: a fifth transistor having a first current electrode coupled to the power supply voltage, a control electrode coupled to the current electrode of the first transistor, and a second current electrode; a sixth transistor having a first current electrode coupled to the power supply voltage, and a second current electrode and a control electrode coupled together; a seventh transistor having a first current electrode and a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the ground; and an eighth transistor having a first current electrode coupled to the second current electrode of the sixth transistor, a control electrode coupled to the second current electrode of the fifth transistor, and a second current electrode coupled to the ground terminal; and a second light sensitive component having first and second terminals both coupled to the second current electrode of the fifth transistor.
15 . The bias circuit of claim 14 , wherein the first and second light sensitive components each comprise an N-well resistor.
16 . The bias circuit of claim 15 , wherein the N-well resistors of the first and second light sensitive components are formed in a P-substrate, and wherein the P-substrate is grounded.
17 . The bias circuit of claim 16 , wherein one or both of an area and resistance value of the second light sensitive component is proportional to one or both an area and resistance value of the first light sensitive component.
18 . The bias circuit of claim 14 , wherein the first circuit is implemented in an unpackaged integrated circuit of a radio frequency identification tag.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the priority under 35 U.S.C. § 119 of European Patent application no. 23306899.8, filed on Nov. 2, 2023, the contents of which are incorporated by reference herein. BACKGROUND Field This disclosure relates generally to electronic circuits, and more particularly, to compensation for light-induced current in an integrated circuit. Related Art Radio-frequency identification (RFID) tags, commonly referred to as RFID inlays, labels or transponders, are widely used to identify an object to which the tag is attached. The most common application examples of RFID tags are retail, supply chain management, shipping services, airline luggage tracking, laundry services, etc. An RFID tag typically includes an antenna and an integrated circuit (IC) (commonly referred to herein as a “chip”). In some RFID tags, the chip is not packaged, or covered, thus exposing the chip to light. RFID tag operation can be dramatically reduced when the tag is exposed to different types of light sources, such as day light, halogen light, light emitting diode (LED) light, etc. In the semiconductor material of the unpackaged chip, light photons can create electron-hole pairs, which generate charge carriers. The photo-generated charge carriers may diffuse through the backside of the semiconductor substrate and part of them may reach pn junctions resulting in a reverse current flow (or photocurrent) which may disturb the operation of some low power circuits on the chip. Many circuits on an IC require a constant bias voltage and/or current in order to operate properly, and the ability of a bias circuit to provide the constant bias voltage and/or current may be adversely affected by the light exposure. FIG. 1 illustrates bias circuit 100 as an example of the above-described disturbance provoked by light exposure. Bias circuit 100 includes two P-channel metal-oxide semiconductor (PMOS) transistors 102 and 103, two N-channel metal-oxide semiconductor (NMOS) transistors 104 and 105, and one N-well resistor 106. Output circuit 101 includes multiple output transistors 107 to deliver multiple bias currents to different circuits of the chip. The bias current presented in bias circuit 100 is generated through a gate-source voltage difference between transistors 104 and 105, which is applied over the N-well resistor 106. The bias current generated in bias circuit 100 is mirrored to the output circuit 101 through a current mirror formed by transistors 102 and any one of output transistors 107. The generated bias current is a resistive current labeled IR. Since N-well resistor 106 is formed with N-well material in a P-substrate, a parasitic pn junction device created by the N-well and P-substrate semiconductor material is present in resistor 106. This means when the N-well resistor is exposed to light, a parallel current at N-well resistor 106 may occur due to the reverse current flow across the pn junction. This parallel current at N-well resistor 106 is a light induced photocurrent, labeled IL, and once generated by a source of light will be added to current IR, resulting in output currents at 107 with the value IR plus IL labeled IR+IL in FIG. 1. The additional current IL flowing from the output devices 107 to different circuits of the chip may increase the overall current consumption of the chip and disturb the operation of circuits receiving current from transistors 107, which would also receive light induced current IL. SUMMARY In accordance with a first aspect of the present disclosure, a circuit implemented on an integrated circuit is provided, the circuit comprising: a first circuit having a first light sensitive circuit component, and an output terminal for providing a first current, wherein at least a portion of the first current is a function of the first light sensitive circuit component; and a compensation circuit having a current mirror and a second light sensitive circuit component, the current mirror having an input terminal coupled to receive a second current that is mirrored from the first current, and an output terminal coupled to provide a third current in response to the second current, the second light sensitive circuit component configured to match the first light sensitive circuit component and to compensate for a light induced current provided by the first light sensitive circuit component, thereby providing the third current without a light induced current component due to the first light sensitive circuit component. In one or more embodiments, the first and second light sensitive components each comprise an N-well resistor. In one or more embodiments, the N-well resistor is formed in a P-substrate, wherein the P-substrate is grounded. In one or more embodiments, one or both of an area and resistance value of the second light sensitive component is proportional to one or both of an area and resistance value of the first light sensitive component. In one or more embodim