US-12620051-B2 - Apparatus and method for biased BVH traversal path

Abstract

Apparatus and method for a biased BVH traversal path. For example, one embodiment of an apparatus comprises: ray tracing traversal hardware logic to traverse a ray through nodes of a bounding volume hierarchy (BVH); and stack management hardware logic to push and pop entries on a traversal stack, each entry corresponding to a node of the BVH, wherein the ray tracing traversal hardware logic is to determine an order in which to push entries to the traversal stack based on both a first intersection value corresponding to a closest intersection point between the ray and a BVH node and a farthest intersection value between the ray and the BVH node. In addition, the ray traversal hardware logic may determine the order in which to push the entries to the traversal stack further based on a probability density value corresponding to a probability of a ray hitting geometry inside of the BVH.

Inventors

• Joshua Barczak
• Sven Woop
• Pawel Majewski
• Radoslaw DRABINSKI

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20220318

Claims (18)

1. 1 . An apparatus comprising: ray tracing traversal hardware logic to traverse a ray through nodes of a bounding volume hierarchy (BVH); and stack management hardware logic to push and pop entries of a traversal stack, each entry corresponding to a node of the BVH, wherein the ray tracing traversal hardware logic is to determine an order in which to push entries to the traversal stack based on: a first intersection value corresponding to a closest intersection point between the ray and a BVH node, a second intersection value corresponding to a farthest intersection point between the ray and the BVH node, and a probability density value corresponding to a probability of a ray hitting geometry inside of each BVH node.
2. 2 . The apparatus of claim 1 wherein for a given BVH node, the ray tracing traversal hardware logic is to determine an intersection distance value based on the probability density value, and is to compare the intersection distance value with intersection distance values of one or more other BVH nodes to determine the order in which to push entries to the traversal stack.
3. 3 . The apparatus of claim 1 wherein the probability density value is used as a likelihood that an object within a given BVH node includes a geometry closer to an origin of the ray than a surface of the BVH node.
4. 4 . The apparatus of claim 1 wherein the ray tracing traversal hardware logic is to determine the order in which to push entries to the traversal stack based on a distance value determined for each of a plurality of the BVH nodes, the distance value based, at least in part, on a difference between the first intersection value and the second intersection value.
5. 5 . The apparatus of claim 4 wherein the distance value is to be determined for each BVH based on both the difference between the first intersection value and the second intersection value and a probability density value corresponding to a probability of a ray hitting geometry inside of each BVH node.
6. 6 . The apparatus of claim 5 wherein with a first probability density value that is larger than a second probability density value, the first probability density value is to produce a first distance value that is smaller than a second distance value produced by the second probability density value; and wherein with a first difference between the first intersection value and the second intersection value that is larger than a second difference between a third intersection value and a fourth intersection value, the first difference is to produce a third distance value larger than a fourth distance value produced by the second difference.
7. 7 . A method comprising: traversing a ray through nodes of a bounding volume hierarchy (BVH) by ray tracing traversal hardware logic; pushing and popping entries of a traversal stack, each entry corresponding to a node of the BVH; and determining an order in which to push entries to the traversal stack based on: a first intersection value corresponding to a closest intersection point between the ray and a BVH node, a second intersection value corresponding to a farthest intersection point between the ray and the BVH node, and a probability density value corresponding to a probability of a ray hitting geometry inside of each BVH node.
8. 8 . The method of claim 7 further comprising: determining, for a given BVH node, an intersection distance value based on the probability density value, and comparing the intersection distance value with intersection distance values of one or more other BVH nodes to determine the order in which to push entries to the traversal stack.
9. 9 . The method of claim 7 wherein the probability density value is used as a likelihood that an object within a given BVH node includes a geometry closer to an origin of the ray than a surface of the BVH node to the origin of the ray.
10. 10 . The method of claim 7 wherein the order in which to push entries to the traversal stack is determined based on a distance value determined for each of a plurality of the BVH nodes, the distance value based, at least in part, on a difference between the first intersection value and the second intersection value.
11. 11 . The method of claim 10 wherein the distance value is to be determined for each BVH based on both the difference between the first intersection value and the second intersection value and a probability density value corresponding to a probability of a ray hitting geometry inside of each BVH node.
12. 12 . The method of claim 11 wherein with a first probability density value that is larger than a second probability density value, the first probability density value is to produce a first distance value that is smaller than a second distance value produced by the second probability density value; and wherein with a first difference between the first intersection value and the second intersection value that is larger than a second difference between a third intersection value and a fourth intersection value, the first difference is to produce a third distance value larger than a fourth distance value produced by the second difference.
13. 13 . A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform: traversing a ray through nodes of a bounding volume hierarchy (BVH) by ray tracing traversal hardware logic; pushing and popping entries of a traversal stack, each entry corresponding to a node of the BVH; and determining an order in which to push entries to the traversal stack based on: a first intersection value corresponding to a closest intersection point between the ray and a BVH node, a second intersection value corresponding to a farthest intersection point between the ray and the BVH node, and a probability density value corresponding to a probability of a ray hitting geometry inside of each BVH node.
14. 14 . The non-transitory machine-readable medium of claim 13 further comprising: determining, for a given BVH node, an intersection distance value based on the probability density value, and comparing the intersection distance value with intersection distance values of one or more other BVH nodes to determine the order in which to push entries to the traversal stack.
15. 15 . The non-transitory machine-readable medium of claim 5 wherein the probability density value is used as a likelihood that an object within a given BVH node includes a geometry closer to an origin of the ray than a surface of the BVH node to the origin of the ray.
16. 16 . The non-transitory machine-readable medium of claim 13 wherein the order in which to push entries to the traversal stack is determined based on a distance value determined for each of a plurality of the BVH nodes, the distance value based, at least in part, on a difference between the first intersection value and the second intersection value.
17. 17 . The non-transitory machine-readable medium of claim 16 wherein the distance value is to be determined for each BVH based on both the difference between the first intersection value and the second intersection value and a probability density value corresponding to a probability of a ray hitting geometry inside of each BVH node.
18. 18 . The non-transitory machine-readable medium of claim 17 wherein with a first probability density value that is larger than a second probability density value, the first probability density value is to produce a first distance value that is smaller than a second distance value produced by the second probability density value; and wherein with a first difference between the first intersection value and the second intersection value that is larger than a second difference between a third intersection value and a fourth intersection value, the first difference is to produce a third distance value larger than a fourth distance value produced by the second difference.

Description

BACKGROUND Field of the Invention This invention relates generally to the field of graphics processors. More particularly, the invention relates to an apparatus and method for biased BVH traversal path. Description of the Related Art Ray tracing is a technique in which a light transport is simulated through physically-based rendering. Widely used in cinematic rendering, it was considered too resource-intensive for real-time performance until just a few years ago. One of the key operations in ray tracing is processing a visibility query for ray-scene intersections known as “ray traversal” which computes ray-scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH). Rasterization is a technique in which, screen objects are created from 3D models of objects created from a mesh of triangles. The vertices of each triangle intersect with the vertices of other triangles of different shapes and sizes. Each vertex has a position in space as well as information about color, texture and its normal, which is used to determine the way the surface of an object is facing. A rasterization unit converts the triangles of the 3D models into pixels in a 2D screen space and each pixel can be assigned an initial color value based on the vertex data. BRIEF DESCRIPTION OF THE DRAWINGS A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which: FIG. 1 is a block diagram of a processing system, according to an embodiment. FIG. 2A is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor. FIG. 2B is a block diagram of hardware logic of a graphics processor core block, according to some embodiments described herein. FIG. 2C illustrates a graphics processing unit (GPU) that includes dedicated sets of graphics processing resources arranged into multi-core groups. FIG. 2D is a block diagram of general-purpose graphics processing unit (GPGPU) that can be configured as a graphics processor and/or compute accelerator, according to embodiments described herein. FIG. 3A is a block diagram of a graphics processor, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores, or other semiconductor devices such as, but not limited to, memory devices or network interfaces. FIG. 3B illustrates a graphics processor having a tiled architecture, according to embodiments described herein. FIG. 3C illustrates a compute accelerator, according to embodiments described herein. FIG. 4 is a block diagram of a graphics processing engine of a graphics processor in accordance with some embodiments. FIG. 5A illustrates graphics core cluster, according to an embodiment. FIG. 5B illustrates a vector engine of a graphics core, according to an embodiment. FIG. 5C illustrates a matrix engine of a graphics core, according to an embodiment. FIG. 6 illustrates a tile of a multi-tile processor, according to an embodiment. FIG. 7 is a block diagram illustrating graphics processor instruction formats according to some embodiments. FIG. 8 is a block diagram of another embodiment of a graphics processor. FIG. 9A is a block diagram illustrating a graphics processor command format that may be used to program graphics processing pipelines according to some embodiments. FIG. 9B is a block diagram illustrating a graphics processor command sequence according to an embodiment. FIG. 10 illustrates an exemplary graphics software architecture for a data processing system according to some embodiments. FIG. 11A is a block diagram illustrating an IP core development system that may be used to manufacture an integrated circuit to perform operations according to an embodiment. FIG. 11B illustrates a cross-section side view of an integrated circuit package assembly 1170, according to some embodiments described herein. FIG. 11C illustrates a package assembly that includes multiple units of hardware logic chiplets connected to a substrate. FIG. 11D illustrates a package assembly including interchangeable chiplets, according to an embodiment. FIG. 12 is a block diagram illustrating an exemplary system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 13 illustrates an exemplary graphics processor of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 14 illustrates an additional exemplary graphics processor 1340 of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 15 illustrates an architecture for performing initial training of a machine-learning architecture; FIG. 16 illustrates how a machine-learning engine is continually trained and updated during runtime; FIG. 17 illustrates how a machine-