US-12620081-B2 - Semiconductor pattern overlay error determination using weighting map based on optical transmission degree through overlying layer

US12620081B2US 12620081 B2US12620081 B2US 12620081B2US-12620081-B2

Abstract

An image of a sample captured by a microscope includes a first layer template image and a second layer template image indicating pattern shapes of a first layer and a second layer. Pattern matching of the second layer is performed based on the second layer template image to acquire a second position deviation amount related to the second layer and an area recognized as the second layer. Pattern matching processing of the first layer is performed based on a first layer consideration range, the first layer template image, and the image to acquire a first position deviation amount related to the first layer and an area recognized as the first layer on the image to be measured. An overlay is measured based on the second position deviation amount and the first position deviation amount.

Inventors

Takahiro Nishihata
Atsushi Miyamoto
Takuma Yamamoto
Yasunori Goto

Assignees

HITACHI HIGH-TECH CORPORATION

Dates

Publication Date: 20260505
Application Date: 20230825
Priority Date: 20220926

Claims (20)

1 . A semiconductor observation system comprising: a microscope and a processor that measures an overlay between a first layer that is a certain layer of a sample formed with two or more layers and a second layer that is one or more layers above the first layer, wherein the processor acquires an image of the sample that is captured by the microscope, acquires a first degree that indicates a degree in which the second layer overlaps the first layer, acquires a first layer template image indicating a pattern shape of the first layer and a second layer template image indicating a pattern shape of the second layer, performs pattern matching processing of the second layer based on the second layer template image and the acquired image to acquire a second position deviation amount related to the second layer and an area recognized as the second layer on the acquired image, the second position deviation amount being a position deviation amount between the second layer template image related to the second layer and the acquired image, determines a first layer consideration range that is a range of pixels of the acquired image considered in pattern matching processing of the first layer based on the first degree and the area recognized as the second layer, performs pattern matching processing of the first layer based on the first layer consideration range, the first layer template image, and the acquired image, to acquire a first position deviation amount related to the first layer and an area recognized as the first layer on the acquired image, the first position deviation amount being a position deviation amount between the first layer template image related to the first layer and the acquired image, and measures an overlay based on the second position deviation amount and the first position deviation amount.
2 . The semiconductor observation system according to claim 1 , wherein the sample includes a third layer that is one or more layers below the first layer, and the processor acquires a second degree indicating a degree in which each layer of the second layer and the first layer overlaps the third layer, acquires a third layer template image indicating a pattern shape of the third layer, determines a third layer consideration range that is a range of pixels of the acquired image considered in pattern matching processing of a third layer based on the second degree, an area recognized as the first layer, and an area recognized as the second layer, performs pattern matching processing of the third layer based on the third layer consideration range, the third layer template image, and the acquired image to acquire a third position deviation amount related to the third layer and an area recognized as the third layer on the acquired image, the third position deviation amount being a position deviation amount between the third layer template image related to the third layer and the acquired image, and measures an overlay based on the third position deviation amount, the first position deviation amount, and the second position deviation amount.
3 . The semiconductor observation system according to claim 1 , wherein the first degree is a value that can be a value of at least less than an upper limit value and equal to or more than a lower limit value, and relates to an area where the second layer covers the first layer, the upper limit value means that the second layer that covers the first layer is not reflected on the acquired image, and the lower limit value means that the first layer covered with the second layer is not reflected in the acquired image.
4 . The semiconductor observation system according to claim 1 , wherein the first degree is a value that can be an upper limit value or a lower limit value, and relates to an area where the second layer covers the first layer, the upper limit value means that the second layer that covers the first layer is not reflected on the acquired image, and the lower limit value means that the first layer covered with the second layer is not reflected on the acquired image.
5 . The semiconductor observation system according to claim 1 , wherein the first degree is a real value a when luminance x of an area where the second layer and the first layer overlap each other in the acquired image is indicated by a linear sum using luminance x1 of the first layer, luminance x2 of the second layer, and a coefficient α.
6 . The semiconductor observation system according to claim 1 , wherein the second layer template image and the first layer template image are design data having layout information of a pattern of each layer of the sample.
7 . The semiconductor observation system according to claim 1 , wherein the second layer template image and the first layer template image are at least one of the following: a line drawing image generated based on design data having area information of a pattern of each layer of the sample, and an image created by simulating an appearance of the acquired image based on the design data.
8 . The semiconductor observation system according to claim 1 , wherein the second layer template image and the first layer template image are generated based on image averaging of a plurality of acquired images.
9 . The semiconductor observation system according to claim 1 , wherein the second layer template image and the first layer template image are images obtained by performing layer recognition processing by using luminance information with respect to an image generated based on image averaging of a plurality of acquired images to separate the images into second layers and first layers.
10 . The semiconductor observation system according to claim 1 , wherein the first layer consideration range is represented by data having the same number of pixels as the acquired image, and each pixel has a value corresponding to the first degree.
11 . The semiconductor observation system according to claim 1 , wherein the pattern matching processing includes calculating a matching score based on a normalized cross-correlation value between the acquired image and the first layer template image over the range of the pixels of the acquired image to calculate a position where the matching score becomes maximum as a pattern position.
12 . The semiconductor observation system according to claim 1 , wherein the first degree is indicated by a luminance change caused by etching of the sample.
13 . The semiconductor observation system according to claim 1 , wherein arrangement of the second layer and the first layer is not from the upper layer to the lower layer, but from the lower layer to the upper layer, and the pattern matching processing is performed from the lower layer to the upper layer.
14 . The semiconductor observation system according to claim 1 , wherein the first degree is displayed on a graphical user interface (GUI) screen and can be confirmed and edited by a user.
15 . An overlay measurement method performed by a processor that measures an overlay between a first layer that is a certain layer of a sample formed with two or more layers and a second layer that is one or more layers above the first layer, the method comprising: acquiring an image of the sample; acquiring a first degree that indicates a degree in which the second layer overlaps the first layer; acquiring a first layer template image indicating a pattern shape of the first layer and a second layer template image indicating a pattern shape of the second layer; performing pattern matching processing of the second layer based on the second layer template image and the acquired image to acquire a second position deviation amount related to the second layer and an area recognized as the second layer on the acquired image, the second position deviation amount being a position deviation amount between the second layer template image related to the second layer and the acquired image; determining a first layer consideration range that is a range of pixels of the acquired image considered in pattern matching processing of the first layer based on the first degree and the area recognized as the second layer; performing pattern matching processing of the first layer based on the first layer consideration range, the first layer template image, and the acquired image, to acquire a first position deviation amount related to the first layer and an area recognized as the first layer on the acquired image, the first position deviation amount being a position deviation amount between the first layer template image related to the first layer and the acquired image; and measuring an overlay based on the second position deviation amount and the first position deviation amount.
16 . The overlay measurement method according to claim 15 , wherein the sample includes a third layer that is one or more layers below the first layer, a second degree indicating a degree in which each layer of the second layer and the first layer overlaps the third layer is acquired, a third layer template image indicating a pattern shape of the third layer is acquired, a third layer consideration range that is a range of pixels of the acquired image considered in pattern matching processing of a third layer based on the second degree, an area recognized as the first layer, and an area recognized as the second layer is determined, pattern matching processing of the third layer is performed based on the third layer consideration range, the third layer template image, and the acquired image to acquire a third position deviation amount related to the third layer and an area recognized as the third layer on the acquired image, the third position deviation amount being a position deviation amount between the third layer template image related to the third layer and the acquired image, and an overlay is measured based on the third position deviation amount, the first position deviation amount, and the second position deviation amount.
17 . The overlay measurement method according to claim 15 , wherein the first degree is a value that can take a value of at least less than an upper limit value and equal to or more than a lower limit value, and relates to an area where the second layer covers the first layer, the upper limit value means that the second layer that covers the first layer is not reflected on the acquired image, and the lower limit value means that the first layer covered with the second layer is not reflected in the acquired image.
18 . The overlay measurement method according to claim 15 , wherein the first degree is a value that can be an upper limit value or a lower limit value, and relates to an area where the second layer covers the first layer, the upper limit value means that the second layer that covers the first layer is not reflected on the acquired image, and the lower limit value means that the first layer covered with the second layer is not reflected on the acquired image.
19 . The overlay measurement method according to claim 15 , wherein the first degree is a real value a when luminance x of an area where the second layer and the first layer overlap each other in the acquired image is indicated by a linear sum using luminance x1 of the first layer, luminance x2 of the second layer, and a coefficient α.
20 . The overlay measurement method according to claim 15 , wherein the second layer template image and the first layer template image are design data having layout information of a pattern of each layer of the sample.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a measurement device of a semiconductor pattern and a computer program, particularly to an overlay measurement device that measures a dimension of a pattern and an overlay error of patterns between a plurality of layers based on an image obtained by a charged particle beam device or the like. 2. Description of Related Art Patterns manufactured by recent semiconductor processes become finer and have a multilayer structure, and there is a demand for reducing overlay errors (hereinafter simply referred to as overlay) of patterns throughout a plurality of layers of an exposure device. Therefore, it is considered that the importance of measuring the overlay with high precision and feeding back to the exposure device will become more important. A scanning electron microscope (SEM), which is a type of charged particle beam device, is widely used as means of such overlay measurement. The SEM outputs a captured image (hereinafter, referred to as an image to be measured) by detecting reflected electrons and the like obtained when an electron beam is irradiated onto a semiconductor sample. Overlay measurement becomes possible by performing appropriate image processing on the image to be measured and calculating a position of a pattern on each layer to be a target of the overlay measurement. There are mainly two methods for calculating a position of a pattern on each layer by image processing. One is a method of performing pattern matching for each layer between a template image and an image to be measured and calculating the position where the matching score becomes maximum as the position of the pattern of each layer. The other is a method of detecting edges of the pattern on each layer by focusing on the luminance change at an edge portion of the pattern on the image to be measured and calculating a center position of the edges as the position of the pattern on each layer. Which method is better depending on the image to be measured. However, in general, the latter method is effective for cases where the edges of the pattern to be measured are sharp, and conversely, the former method is effective for cases where the edges of the pattern to be measured are unclear or some of the edges of the pattern in a layer of interest are hidden by other layers. The present invention is directed to the former, and the following description is based on pattern matching processing of the former. In general, patterns of a plurality of layers are seen through the overlay image to be measured. Thereby, there are cases where a part of the pattern in the lower layer to be measured is hidden by the upper layer, resulting in a lower matching score and matching failure, and cases where the pattern is erroneously matched with a pattern in an untargeted layer. To reduce such pattern matching failures, processing of excluding information on layers unrelated to the layer to be measured during pattern matching calculation is effective. There are JP2013-168595A and JP2011-90470A as related art in the technical field. JP2013-168595A discloses performing area division processing on an upper layer pattern and a lower layer pattern depending on luminance information with respect to each of a template image and an image to be measured and performing pattern matching between the upper layer pattern areas and between the lower layer pattern areas for each of the template image and the image to be measured. JP2011-90470A discloses a method of using design data of a sample to be measured to generate a mask processing area that is not taken into consideration during pattern matching by using edge information of the design data. Both methods can reduce failures in pattern matching by not using layer information unrelated to the layer to be measured. According to the multi-layered structuring of the semiconductor pattern, there are cases where low-energy electron beams in the related art cannot reveal the pattern of the lower layer, and thus a high-acceleration SEM that irradiates with high-energy electron beams (for example, 15 keV or higher) have begun to be used for overlay measurements, in recent years. In the image to be measured by the high-acceleration SEM, there are cases where the lower layer can be seen through the upper layer due to the height of energy of the electron beam. For the image to be measured in which the overlapping portion of the upper layer and the lower layer is transmissive, if the area division or the mask processing disclosed in JP2013-168595A or JP2011-90470A is carelessly performed to remove information of the upper layer area at the time of pattern matching of the lower layer, the information of the lower layer that transmits through the upper layer is erased, and thus a pattern matching success rate may be rather deteriorated. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to improve a success