US-12620328-B2 - Source driver reducing test time by simultaneously performing test on the source driver and display driver integrated circuit including the same

US12620328B2US 12620328 B2US12620328 B2US 12620328B2US-12620328-B2

Abstract

A display driving integrated circuit includes: a gamma voltage generator outputs a plurality of gamma voltages at a first voltage level based on a first control signal in a first time period among a plurality of time periods, outputs a plurality of gamma voltages at a second voltage level based on a second control signal in a second time period among the plurality of time periods, and outputs a reference voltage that swings between a third voltage level lower than the first voltage level and a fourth voltage level higher than the second voltage level in the plurality of time periods; and a source block circuit receives input data in response to a first clock signal in the first time period, selects a first gamma voltage among the plurality of gamma voltages of the first voltage level based on the input data, and compares the first gamma voltage and the reference voltage.

Inventors

Taek Su KWON
In-Suk Kim
Jeeyeon EOM

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20240815
Priority Date: 20231219

Claims (20)

1 . A display driving integrated circuit comprising: a gamma voltage generator configured to in a first mode, output a plurality of gamma voltages at a plurality of voltage levels, in a second mode, output the plurality of gamma voltages at a first voltage level among the plurality of voltage levels based on a first control signal in a plurality of first time periods among a plurality of time periods, in the second mode, output the plurality of gamma voltages at a second voltage level among the plurality of voltage levels based on a second control signal in time periods other than the plurality of first time periods among the plurality of time periods, and in the second mode, output a reference voltage that swings between a third voltage level lower than the first voltage level and a fourth voltage level higher than the second voltage level in the plurality of time periods; and a source block circuit configured to in the first mode, amplify the plurality of gamma voltages, in the second mode, receive input data in response to a first clock signal in the plurality of first time periods, in the second mode, select a first gamma voltage among the plurality of gamma voltages of the first voltage level based on the input data, and in the second mode, compare the first gamma voltage and the reference voltage.
2 . The display driving integrated circuit of claim 1 , further comprising a plurality of registers configured to receive an output signal as a result of the comparison between the first gamma voltage and the reference voltage, and detect a voltage level of the output signal based on a second clock signal that is different from the first clock signal.
3 . The display driving integrated circuit of claim 2 , wherein the plurality of registers are configured to determine a predicted voltage level of the output signal based on the first control signal and the second control signal, and determine whether the source block circuit is defective based on the predicted voltage level and the voltage level of the output signal when the second clock signal transitions to a first level.
4 . The display driving integrated circuit of claim 3 , wherein the second clock signal transitions to the first voltage level at a time point delayed by a predetermined time from a time point when the first clock signal transitions to the first voltage level.
5 . The display driving integrated circuit of claim 3 , wherein subsequent to determining that the source block circuit is defective, the plurality of registers are configured to further detect the voltage level of the output signal at a time point delayed by a predetermined time from the time point when the second clock signal transitions to the first voltage level.
6 . The display driving integrated circuit of claim 2 , wherein the source block circuit includes a decoder configured to select the first gamma voltage of the plurality of gamma voltages based on the input data, a comparator configured to compare the first gamma voltage and the reference voltage to output a first signal, and a level shifter configured to level-shift the first signal to generate the output signal.
7 . The display driving integrated circuit of claim 6 , wherein the source block circuit further includes a first switch connecting the comparator and the gamma voltage generator, a second switch connecting an output terminal of the comparator and an input terminal of the comparator, and a third switch connecting the comparator and the level shifter.
8 . The display driving integrated circuit of claim 7 , wherein in the plurality of first time periods and the time periods other than the plurality of first time periods among the plurality of time periods, the first switch and the third switch are closed and the second switch is opened.
9 . The display driving integrated circuit of claim 1 , wherein the gamma voltage generator includes a first resistor string configured to generate the plurality of gamma voltages, a first plurality of switches connected between a first line of the first voltage level and the first resistor string, and a second plurality of switches connected between a second line of the second voltage level and the first resistor string.
10 . The display driving integrated circuit of claim 9 , wherein the gamma voltage generator further includes a second resistor string configured to divide a first voltage of the first voltage level and a second voltage of the second voltage level to generate a plurality of reference gamma voltages; a plurality of gamma decoders configured to output the plurality of reference gamma voltages, respectively; and a plurality of gamma amplifiers configured to receive the plurality of reference gamma voltages respectively from the plurality of gamma decoders, wherein the plurality of gamma amplifiers are connected to the first resistor string, and are disabled in the plurality of first time periods and the time periods other than the plurality of first time periods among the plurality of time periods.
11 . The display driving integrated circuit of claim 10 , wherein the gamma voltage generator further includes a reference voltage amplifier configured to receive one of the plurality of reference gamma voltages from a first gamma decoder of the plurality of gamma decoders and output the reference voltage.
12 . The display driving integrated circuit of claim 9 , wherein the first plurality of switches are configured to close based on the first control signal, the second plurality of switches are configured to close based on the second control signal, and the first control signal and the second control signal are inverted with respect to each other.
13 . A source driver comprising: a decoder configured to select a first gamma voltage of a first plurality of gamma voltages based on input data in a first mode and select a second gamma voltage of a second plurality of gamma voltages based on input data in a second mode; a comparator configured to amplify the first gamma voltage in the first mode to generate a data signal corresponding to the input data, and compare the second gamma voltage and a reference voltage in the second mode to generate a comparison signal; and a level shifter configured to shift a level of the comparison signal in the second mode to generate an output signal.
14 . The source driver of claim 13 , wherein a voltage level of the second plurality of gamma voltages is a first level or a second level different from the first level.
15 . The source driver of claim 14 , wherein the reference voltage swings between a third level lower than the first level and a fourth level higher than the second level.
16 . The source driver of claim 13 , further comprising a plurality of registers configured to output the input data based on a first clock signal in the first mode and detect a voltage level of the output signal based on a second clock signal that is different from the first clock signal in the second mode.
17 . The source driver of claim 16 , wherein the second clock signal transitions to an enable level at a time point delayed by a predetermined time from a time point when the first clock signal transitions to the enable level.
18 . A display driving integrated circuit comprising: a source block circuit configured to receive a plurality of gamma voltages at a maximum gamma voltage level in a first time period, receive input data based on a first clock signal, select a first gamma voltage of the plurality of gamma voltages at the maximum gamma voltage level based on the input data, compare the first gamma voltage and a reference voltage to generate a first output signal, receive a plurality of gamma voltages at a minimum gamma voltage level in a second time period, select a second gamma voltage of the plurality of gamma voltages at the minimum gamma voltage level based on the input data, and compare the second gamma voltage and the reference voltage to generate a second output signal; a plurality of registers configured to receive the first output signal and the second output signal, detect a voltage level of the first output signal based on a second clock signal that is different from the first clock signal in the first time period, and detect a voltage level of the second output signal based on the second clock signal in the second time period; and a driving controller configured to output the first clock signal and the second clock signal.
19 . The display driving integrated circuit of claim 18 , wherein the plurality of registers are configured to predict the voltage level of the first output signal based on the plurality of gamma voltages at the maximum gamma voltage level in the first time period, and determine whether the source block circuit is defective based on the predicted voltage level of the first output signal and the detected voltage level of the first output signal.
20 . The display driving integrated circuit of claim 19 , wherein when it is determined that the source block circuit is defective, the plurality of registers are configured to further receive a third clock signal different from the second clock signal from the driving controller.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0185969 filed in the Korean Intellectual Property Office on Dec. 19, 2023, the entire content of which is incorporated herein by reference. BACKGROUND Generally, a display panel provides various visual information to a user by displaying an image. The display panel includes a plurality of pixels, and each of the plurality of pixels expresses light of a predetermined luminance to display an image. A display driver integrated circuit (DDI) is used to drive the pixel. Meanwhile, it is possible to determine whether the DDI is defective through an electrical die sorting (EDS) test, which is one of test processes for wafers. However, as the number of channels in DDI increases, the EDS test time also increases. Therefore, various studies are being actively conducted to reduce the EDS test time. SUMMARY The present disclosure relates to a source driver and a display driver integrated circuit including the same. According to some implementations, a source driver may determine defects in the source driver and a display driver integrated circuit including the same. According to some implementations, a source driver may reduce a test time by simultaneously performing a test on the source driver and a display driver integrated circuit including the same. According to some implementations, a display driving integrated circuit includes: a gamma voltage generator-configured to output a plurality of gamma voltages at a first voltage level based on a first control signal in a first time period among a plurality of time periods, output a plurality of gamma voltages at a second voltage level based on a second control signal in a second time period among the plurality of time periods, and output a reference voltage that swings between a third voltage level lower than the first voltage level and a fourth voltage level higher than the second voltage level in the plurality of time periods; and a source block circuit configured to receive input data in response to a first clock signal in the first time period, select a first gamma voltage among the plurality of gamma voltages of the first voltage level based on the input data, and compare the first gamma voltage and the reference voltage. According to some implementations, a source driver includes: a decoder configured to select a first gamma voltage of a first plurality of gamma voltages based on input data in a first mode and select a second gamma voltage of a second plurality of gamma voltages based on input data in a second mode; a comparator configured to amplify the first gamma voltage in the first mode to generate a data signal corresponding to the input data, and compare the second gamma voltage and a reference voltage in the second mode to generate a comparison signal; and a level shifter configured to shift a level of the comparison signal in the second mode to generates an output signal. According to some implementations, a display driving integrated circuit includes: a source block circuit configured to receive a plurality of gamma voltages at a maximum gamma voltage level in a first time period, receive input data based on a first clock signal, selects a first gamma voltage of the plurality of gamma voltages at the maximum gamma voltage level based on the input data, compare the first gamma voltage and a reference voltage to generate a first output signal, receive a plurality of gamma voltages at a minimum gamma voltage level in a second time period, select a second gamma voltage of the plurality of gamma voltages at the minimum gamma voltage level based on the input data, and compare the second gamma voltage and the reference voltage to generate a second output signal; a plurality of registers configured to receive the first output signal and the second output signal, detect a voltage level of the first output signal based on a second clock signal that is different from the first clock signal in the first time period, and detect a voltage level of the second output signal based on the second clock signal in the second time period; and a driving controller configured to output the first clock signal and the second clock signal. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a block diagram of a display system according to some implementations. FIG. 2 illustrates an example block diagram of a display device according to some implementations. FIG. 3 illustrates a block diagram of a partial configuration of a source driver according to some implementations. FIG. 4 illustrates an example block diagram of a gamma voltage generator according to some implementations. FIG. 5 illustrates a timing diagram of signals inputted and outputted to a driving controller and a source driver according to some implementations. FIG. 6 illustrates a flowchart of an operation method of a source driver according to some implementations. FIG. 7 illustrates a