US-12620332-B2 - Display panel with regional variable refresh rates and drive method

US12620332B2US 12620332 B2US12620332 B2US 12620332B2US-12620332-B2

Abstract

Provided are a display panel with regional variable refresh rates and a driving method. The display panel includes: a region classification module for detecting in a display region of said panel row information corresponding to a static display region with an invariable picture and to a dynamic display region with a variable picture, and generating control signal groups of corresponding states; and a driving circuit for receiving a first control signal group corresponding to the static display region, so that drive voltages of related pixel rows of the static display region are output to the next row drive circuit, and an output signal of the drive circuit retains at a high level, or receiving a second control signal group corresponding to the dynamic display region, so that drive voltages of related pixel rows of the dynamic display region are output to both the next row drive circuit and the output signal of the drive circuit.

Inventors

Ying-Hsiang TSENG

Assignees

EVERDISPLAY OPTRONICS (SHANGHAI) CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230223
Priority Date: 20221205

Claims (16)

1 . A display panel with regional varying refresh rates, comprising: a driving circuit, configured to receive a first control signal group corresponding to a static display region with invariable pictures in a display area of the display panel, to cause a driving voltage of a relevant pixel row of the static display region to be output to a driving circuit of a next row and cause an output signal of the driving circuit to maintain a high level; or to receive a second control signal group corresponding to a dynamic display region with variable pictures in the display area of the display panel, to cause a driving voltage of a relevant pixel row of the dynamic display region to be output to a driving circuit of a next row and the output signal of the driving circuit, respectively, wherein the driving circuit comprises a plurality of rows of driving units, and the driving unit comprises: a first transistor, wherein a first electrode of the first transistor is coupled to a first power supply voltage, and a gate of the first transistor is coupled to a first node; a second transistor, wherein a first electrode of the second transistor is coupled to a second electrode of the first transistor, a second electrode of the second transistor is coupled to a second node, and a gate of the second transistor is coupled to a first input terminal; a third transistor, wherein a first electrode of the third transistor is coupled to the second node, a second electrode of the third transistor is coupled to a third input terminal, and a gate of the third transistor is coupled to a second input terminal; a fourth transistor, wherein a first electrode of the fourth transistor is coupled to the first node, a second electrode of the fourth transistor is coupled to the second input terminal, and a gate of the fourth transistor is coupled to the second node; a fifth transistor, wherein a first electrode of the fifth transistor is coupled to the first node, a second electrode of the fifth transistor is coupled to a second power supply voltage, and a gate of the fifth transistor is coupled to the second input terminal; a sixth transistor, wherein a first electrode of the sixth transistor is coupled to the first power supply voltage, a second electrode of the sixth transistor is coupled to a third node, and a gate of the sixth transistor is coupled to the first node; a seventh transistor, wherein a first electrode of the seventh transistor is coupled to the third node, a second electrode of the seventh transistor is coupled to the first input terminal, and a gate of the seventh transistor is directly coupled to the second node; an eighth transistor, wherein a first electrode of the eighth transistor is coupled to the third node, and a second electrode of the eighth transistor is directly coupled to an output terminal; a ninth transistor, wherein a first electrode of the ninth transistor is directly coupled to the first power supply voltage, and a second electrode of the ninth transistor is directly coupled to the output terminal; a first capacitor, wherein a first electrode of the first capacitor is coupled to the first power supply voltage, and a second electrode of the first capacitor is coupled to the first node; and a second capacitor, wherein a first electrode of the second capacitor is directly coupled to the second node, and a second electrode of the second capacitor is coupled to the third node; wherein a gate of the eighth transistor is coupled to a fourth input terminal, and a gate of the ninth transistor is coupled to a fifth input terminal.
2 . The display panel with regional varying refresh rates according to claim 1 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are all P-type MOS transistors.
3 . The display panel with regional varying refresh rates according to claim 2 , wherein the gate of the eighth transistor and the gate of the ninth transistor respectively receive a first control signal and a second control signal of the first control signal group.
4 . The display panel with regional varying refresh rates according to claim 3 , wherein the first control signal and the second control signal are signals reverse to each other.
5 . The display panel with regional varying refresh rates according to claim 1 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are P-type MOS transistors, and the eighth transistor is an N-type MOS transistor.
6 . The display panel with regional varying refresh rates according to claim 5 , wherein the gate of the eighth transistor and the gate of the ninth transistor respectively receive the same control signal of the first control signal group.
7 . The display panel with regional varying refresh rates according to claim 1 , wherein the driving circuit further comprises a first signal lead, a second signal lead, a fourth signal lead and a fifth signal lead; the driving voltage of the driving unit in a previous row is output to the third input terminal of the driving unit in the next row as a starting signal; the first input terminal is coupled to the first signal lead; the second input terminal is coupled to the second signal lead; the fourth input terminal is coupled to the fourth signal lead; and the fifth input terminal is coupled to the fifth signal lead.
8 . The display panel with regional varying refresh rates according to claim 7 , wherein the driving circuit further comprises a starting signal lead, and the third input terminal of the driving unit in the first row is coupled to the starting signal lead.
9 . A driving method, applied to a driving circuit of a display panel with regional varying refresh rates, the driving circuit of the display panel being configured to receive a first control signal group corresponding to a static display region with invariable pictures in a display area of the display panel, to cause a driving voltage of a relevant pixel row of the static display region to be output to a driving circuit of a next row and cause an output signal of the driving circuit to maintain a high level, or to receive a second control signal group corresponding to a dynamic display region with variable pictures in the display area of the display panel, to cause a driving voltage of a relevant pixel row of the dynamic display region to be output to a driving circuit of a next row and the output signal of the driving circuit, respectively, the method comprising: in the static display region, receiving, by the driving circuit of the relevant pixel row, a first control signal group sent jointly by a fourth signal lead and a fifth signal lead, and outputting the driving voltage of the driving circuit to the driving circuit of the next row, wherein an output signal of the driving circuit is output at a high level to maintain picture data of the pixel row in a previous frame; and in the dynamic display region, receiving, by the driving circuit of the relevant pixel row, a second control signal group sent jointly by the fourth signal lead and the fifth signal lead, and outputting the driving voltage of the driving circuit to the output signal of the driving circuit and the driving circuit of the next row, respectively, to update the picture data of the pixel row in the previous frame, wherein the driving circuit comprises a plurality of rows of driving units, and the driving unit comprises: a first transistor, wherein a first electrode of the first transistor is coupled to a first power supply voltage, and a gate of the first transistor is coupled to a first node; a second transistor, wherein a first electrode of the second transistor is coupled to a second electrode of the first transistor, a second electrode of the second transistor is coupled to a second node, and a gate of the second transistor is coupled to a first input terminal; a third transistor, wherein a first electrode of the third transistor is coupled to the second node, a second electrode of the third transistor is coupled to a third input terminal, and a gate of the third transistor is coupled to a second input terminal; a fourth transistor, wherein a first electrode of the fourth transistor is coupled to the first node, a second electrode of the fourth transistor is coupled to the second input terminal, and a gate of the fourth transistor is coupled to the second node; a fifth transistor, wherein a first electrode of the fifth transistor is coupled to the first node, a second electrode of the fifth transistor is coupled to a second power supply voltage, and a gate of the fifth transistor is coupled to the second input terminal; a sixth transistor, wherein a first electrode of the sixth transistor is coupled to the first power supply voltage, a second electrode of the sixth transistor is coupled to a third node, and a gate of the sixth transistor is coupled to the first node; a seventh transistor, wherein a first electrode of the seventh transistor is coupled to the third node, a second electrode of the seventh transistor is coupled to the first input terminal, and a gate of the seventh transistor is directly coupled to the second node; an eighth transistor, wherein a first electrode of the eighth transistor is coupled to the third node, and a second electrode of the eighth transistor is directly coupled to an output terminal; a ninth transistor, wherein a first electrode of the ninth transistor is directly coupled to the first power supply voltage, and a second electrode of the ninth transistor is coupled to the output terminal; a first capacitor, wherein a first electrode of the first capacitor is coupled to the first power supply voltage, and a second electrode of the first capacitor is coupled to the first node; and a second capacitor, wherein a first electrode of the second capacitor is directly coupled to the second node, and a second electrode of the second capacitor is coupled to the third node; wherein a gate of the eighth transistor is coupled to a fourth input terminal, and a gate of the ninth transistor is coupled to a fifth input terminal.
10 . The driving method according to claim 9 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are all P-type MOS transistors.
11 . The driving method according to claim 10 , wherein the gate of the eighth transistor and the gate of the ninth transistor respectively receive a first control signal and a second control signal of the first control signal group.
12 . The driving method according to claim 11 , wherein the first control signal and the second control signal are signals reverse to each other.
13 . The driving method according to claim 9 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are P-type MOS transistors, and the eighth transistor is an N-type MOS transistor.
14 . The driving method according to claim 13 , wherein the gate of the eighth transistor and the gate of the ninth transistor respectively receive the same control signal of the first control signal group.
15 . The driving method according to claim 9 , wherein the driving circuit further comprises a first signal lead, a second signal lead, a fourth signal lead and a fifth signal lead; the driving voltage of the driving unit in a previous row is output to the third input terminal of the driving unit in the next row as a starting signal; the first input terminal is coupled to the first signal lead; the second input terminal is coupled to the second signal lead; the fourth input terminal is coupled to the fourth signal lead; and the fifth input terminal is coupled to the fifth signal lead.
16 . The driving method according to claim 15 , wherein the driving circuit further comprises a starting signal lead, and the third input terminal of the driving unit in the first row is coupled to the starting signal lead.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application is a US national phase of International Application No. PCT/CN2023/077890, filed on Feb. 23, 2023, which is based upon and claims priority to Chinese Patent Application No. 202211548369.7, filed on Dec. 5, 2022, the entire contents of both of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to the field of display panel control circuits, and in particular to a display panel with regional varying refresh rates and a driving method. BACKGROUND As a new generation of display technology, an Organic Light Emitting Diode (OLED) display has advantages of low power consumption, high color gamut, high brightness, high refresh rate, wide viewing angle, high response speed, etc. In particular, the advantage of high refresh rate makes OLED display more suitable for display of mobile devices, and therefore it is increasingly widely used. The refresh rate of the display refers to the number of times the image on the screen is repeatedly scanned from top to bottom. The higher the refresh rate, the more stable the displayed image is and the less fatigued the human eyes are. In recent years, as people spend more and more time using mobile devices, the refresh rates of various mobile device displays have been gradually increased in order to provide a better user experience. However, mobile devices have high requirements for power consumption, and the proportion of power consumption occupied by the display is particularly important. The refresh rate of the display directly affects the power consumption. Although a low refresh rate has lower power consumption, the dynamic image display effect with the low refresh rate seriously affects the display quality. At present, when using a mobile device, not all images in respective display regions change in real time. In particular, in the case of short video applications, there are a large number of static display regions in the display area where the images do not change for a long time. However, currently all the display regions of the display of the mobile device employs the same refresh rate, that is, a high refresh rate used for a dynamic display region, resulting in a waste of power consumption. Moreover, always working at the highest refresh rate accelerates aging of the display. SUMMARY In view of the defects in the related arts, the purpose of the present disclosure is to provide a display panel with regional varying refresh rates and a driving method. The embodiments of the present disclosure provide a display panel with regional varying refresh rates, including: an region classification module, configured to detect row information corresponding to a static display region with invariable pictures and a dynamic display region with variable pictures in a display area of the panel, and generate control signal groups for corresponding states; anda driving circuit, configured to receive a first control signal group corresponding to the static display region, to cause a driving voltage of a relevant pixel row of the static display region to be output to a driving circuit of a next row, and cause an output signal of the driving circuit to maintain a high level; or to receive a second control signal group corresponding to the dynamic display region, to cause a driving voltage of a relevant pixel row of the dynamic display region to be output to a driving circuit of a next row and an output signal of the driving circuit, respectively. In some embodiments, the driving circuit includes a plurality of rows of driving units, and the driving unit includes: a first transistor, wherein a first electrode of the first transistor is coupled to a first power supply voltage, and a gate of the first transistor is coupled to a first node;a second transistor, wherein a first electrode of the second transistor is coupled to a second electrode of the first transistor, a second electrode of the second transistor is coupled to a second node, and a gate of the second transistor is coupled to a first input terminal;a third transistor, wherein a first electrode of the third transistor is coupled to the second node, a second electrode of the third transistor is coupled to a third input terminal, and a gate of the third transistor is coupled to a second input terminal;a fourth transistor, wherein a first electrode of the fourth transistor is coupled to the first node, a second electrode of the fourth transistor is coupled to the second input terminal, and a gate of the fourth transistor is coupled to the second node;a fifth transistor, wherein a first electrode of the fifth transistor is coupled to the first node, a second electrode of the fifth transistor is coupled to a second power supply voltage, and a gate of the fifth transistor is coupled to the second input terminal;a sixth transistor, wherein a first electrode of the sixth transistor is coupled to the first power supply voltage, a second electr