US-12620333-B2 - Power management circuit and display device including the same

Abstract

A display device includes a display panel which displays an image, a data driver which provides a data voltage to the display panel, and a power management circuit which provides an analog power voltage to the data driver through an output terminal. The power management circuit measures a load current output through the output terminal, and increases a voltage level of the analog power voltage based on the load current at a first increase time point within a blank period.

Inventors

• Kwanghun KANG

Assignees

• SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date

20260505

Application Date

20241011

Priority Date

20231023

Claims (20)

1. 1 . A display device, comprising: a display panel configured to display an image; a data driver configured to provide a data voltage to the display panel; and a power management circuit configured to generate an analog power voltage and to provide the analog power voltage to the data driver through an output terminal, wherein the power management circuit is configured to measure a magnitude of a load current output through the output terminal and increase a voltage level of the analog power voltage output to the data driver based on the magnitude of the measured load current at a first increase time point within a blank period.
2. 2 . The display device of claim 1 , wherein the power management circuit is configured to: calculate a target voltage level based on the magnitude of the load current, and increase the voltage level of the analog power voltage to the target voltage level at the first increase time point.
3. 3 . The display device of claim 2 , wherein the target voltage level increases as the magnitude of the load current increases.
4. 4 . The display device of claim 1 , wherein the power management circuit is configured to: calculate a target voltage level based on the magnitude of the load current, increase the voltage level of the analog power voltage to an intermediate voltage level lower than the target voltage level at the first increase time point, and increase the voltage level of the analog power voltage to the target voltage level at a second increase time point within the blank period after the first increase time point.
5. 5 . The display device of claim 1 , wherein the first increase time point is after a predetermined delay time from a start time point of the blank period.
6. 6 . The display device of claim 1 , wherein the power management circuit is configured to measure the load current in an active period before the blank period.
7. 7 . The display device of claim 1 , wherein the power management circuit includes: a voltage converter configured to convert an input voltage received through an input terminal to the analog power voltage; and a load sensor configured to measure the magnitude of the load current and provide a voltage signal to the voltage converter corresponding to the magnitude of the measured load current, wherein the voltage converter may be further configured to control the voltage level of the analog power voltage based on the voltage signal received from the load sensor.
8. 8 . The display device of claim 7 , wherein the voltage converter includes: an inductor connected between the input terminal and a node; a first transistor connected between the node and a reference potential and configured to turn-on in response to a first control signal; a second transistor connected between the node and the output terminal and configured to turn-on in response to a second control signal; and a gate driver configured to generate the first control signal and the second control signal.
9. 9 . The display device of claim 8 , wherein the load sensor includes: a half duty generation circuit configured to generate a second voltage based on a first voltage corresponding to a current flowing through the inductor; a sample and hold circuit configured to generate a third voltage by sampling a voltage level of the second voltage at a reference time point within a turn-on period of the second transistor; and a multiplier configured to generate a fourth voltage corresponding to the load current by multiplying a turn-on period of the first transistor by the third voltage.
10. 10 . The display device of claim 7 , wherein the power management circuit further includes: a counter configured to determine the first increase time point by counting a clock signal from a start time point of the blank period.
11. 11 . A power management circuit, comprising: a voltage converter configured to convert an input voltage received through an input terminal to an analog power voltage, and to provide the analog power voltage through an output terminal; and a load sensor configured to measure a magnitude of a load current output through the output terminal, wherein the voltage converter is configured to increase a voltage level of the analog power voltage at a first increase time point within a blank period based on the magnitude of the measured load current.
12. 12 . The power management circuit of claim 11 , wherein the voltage converter is configured to: calculate a target voltage level based on the magnitude of the load current, and increase the voltage level of the analog power voltage to the target voltage level at the first increase time point.
13. 13 . The power management circuit of claim 12 , wherein the target voltage level increases as the magnitude of the load current increases.
14. 14 . The power management circuit of claim 11 , wherein the voltage converter is configured to: calculate a target voltage level based on the magnitude of the load current, increase the voltage level of the analog power voltage to an intermediate voltage level lower than the target voltage level at the first increase time point, and increase the voltage level of the analog power voltage to the target voltage level at a second increase time point within the blank period after the first increase time point.
15. 15 . The power management circuit of claim 11 , wherein the first increase time point is after a predetermined delay time from a start time point of the blank period.
16. 16 . The power management circuit of claim 11 , wherein the load sensor is configured to measure the load current in an active period before the blank period.
17. 17 . The power management circuit of claim 11 , wherein the voltage converter includes: an inductor connected between the input terminal and a node; a first transistor connected between the node and a reference potential and configured to turn-on in response to a first control signal; a second transistor connected between the node and the output terminal and configured to turn-on in response to a second control signal; and a gate driver configured to generate the first control signal and the second control signal.
18. 18 . The power management circuit of claim 17 , wherein the load sensor includes: a half duty generation circuit configured to generate a second voltage based on a first voltage corresponding to a current flowing through the inductor; a sample and hold circuit configured to generate a third voltage by sampling a voltage level of the second voltage at a reference time point within a turn-on period of the second transistor; and a multiplier configured to generate a fourth voltage corresponding to the load current by multiplying a turn-on period of the first transistor by the third voltage.
19. 19 . The power management circuit of claim 11 , further comprising: a counter configured to determine the first increase time point by counting a clock signal from a start time point of the blank period.
20. 20 . The power management circuit of claim 11 , wherein the voltage converter includes a boost converter.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2023-0141971, filed on Oct. 23, 2023, in the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated by reference herein. BACKGROUND 1. Field One or more embodiments described herein relate to a power management circuit and a display device including the power management circuit. 2. Description of the Related Art A display device may include a display panel that displays an image, a data driver that provides data voltages to the display panel, and a power management circuit that provides an analog power voltage to the data driver. The data driver may include a plurality of buffers (or amplifiers) that output the data voltages, and the buffers may output the data voltages using the analog power voltage as an operating voltage (or driving voltage). The power management circuit may output the analog power voltage to the data driver through an output terminal. Depending on the load of the output terminal from which the analog power voltage is output, a ripple may occur in the analog power voltage provided to the data driver. When the ripple occurs in the analog power voltage, the display quality of the display device may be reduced. SUMMARY One or more embodiments described here provide a power management circuit providing an analog power voltage with a reduced ripple. These and/or other embodiments provide a display device with improved display quality and reduced power consumption. A display device according to embodiments may include a display panel which displays an image, a data driver which provides a data voltage to the display panel, and a power management circuit which provides an analog power voltage to the data driver through an output terminal. The power management circuit may measure a load current output through the output terminal, and increase a voltage level of the analog power voltage based on the load current at a first increase time point within a blank period. In an embodiment, the power management circuit may calculate a target voltage level based on a magnitude of the load current, and increase the voltage level of the analog power voltage to the target voltage level at the first increase time point. In an embodiment, the target voltage level may increase as the magnitude of the load current increases. In an embodiment, the power management circuit may calculate a target voltage level based on a magnitude of the load current, increase the voltage level of the analog power voltage to an intermediate voltage level lower than the target voltage level at the first increase time point, and increase the voltage level of the analog power voltage to the target voltage level at a second increase time point within the blank period after the first increase time point. In an embodiment, the first increase time point may be after a predetermined delay time from a start time point of the blank period. In an embodiment, the power management circuit may measure the load current in an active period before the blank period. In an embodiment, the power management circuit includes a voltage converter which converts an input voltage receiving through an input terminal into the analog power voltage, and a load sensor which measures the load current. In an embodiment, the voltage converter may include an inductor connected between the input terminal and a node, a first transistor connected between the node and a ground and turned-on in response to a first control signal, a second transistor connected between the node and the output terminal and turned-on in response to a second control signal, and a gate driver which generates the first control signal and the second control signal. In an embodiment, the load sensor may include a half duty generation circuit which generates a second voltage based on a first voltage corresponding to a current flowing through the inductor, a sample and hold circuit which generates a third voltage by sampling a voltage level of the second voltage at a reference time point within a turn-on period of the second transistor, and a multiplier which generates a fourth voltage corresponding to the load current by multiplying a turn-on period of the first transistor by the third voltage. In an embodiment, the power management circuit may further include a counter which determines the first increase time point by counting a clock signal from a start time point of the blank period. A power management circuit according to embodiments may include a voltage converter which converts an input voltage receiving through an input terminal into an analog power voltage and provides the analog power voltage through an output terminal, and a load sensor which measures a load current output through the output terminal. The voltage converter may increase a voltage level of the analog power voltage based on the load current at a first increase