US-12620334-B2 - Slew rate enhancement at source amplifier inputs

US12620334B2US 12620334 B2US12620334 B2US 12620334B2US-12620334-B2

Abstract

A display driver includes a plurality of gamma bus lines and a drive leg configured to receive pixel data. The drive leg includes a decoder having first and second outputs, a source amplifier having a set of inputs, and a source interpolation selector. The decoder electrically connects, based on the pixel data, the first output to a first one of the gamma bus lines and the second output to a second one of the gamma bus lines. The source amplifier provides a data voltage to a display panel based on a set of input voltages at the set of inputs. The source interpolation selector provides, based on the pixel data, electrical connections between the first and second outputs of the decoder and the set of inputs of the source amplifier, and electrically connects the first and second outputs of the decoder during a first period of a horizontal sync period.

Inventors

Keita Tsubakino

Assignees

SYNAPTICS INCORPORATED

Dates

Publication Date: 20260505
Application Date: 20250618

Claims (20)

1 . A display driver, comprising: a decoder, wherein the decoder is configured to: electrically couple a first output of the decoder to a first gamma bus line of a plurality of gamma bus lines based on first pixel data provided to the decoder; and electrically couple a second output of the decoder to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data; an amplifier comprising a set of inputs and configured to provide a data voltage to a display panel based on a set of input voltages at the set of inputs; and an interpolation selector configured to: electrically couple the first and second outputs of the decoder to the set of inputs of the amplifier based on the first pixel data; and electrically couple the first and second outputs of the decoder during a first period of a horizontal sync period.
2 . The display driver of claim 1 , further comprising: a drive leg configured to receive the first pixel data and a plurality of gamma voltages.
3 . The display driver of claim 2 , wherein the plurality of gamma voltages is generated on the plurality of gamma bus lines.
4 . The display driver of claim 1 , wherein the interpolation selector is further configured to: electrically couple respective inputs of the amplifier to the first output or the second output of the decoder during a second period of the horizontal sync period, the second period following the first period.
5 . The display driver of claim 1 , wherein the interpolation selector comprises: a first set of switches electrically coupled between the first output of the decoder and the set of inputs of the amplifier, respectively; and a second set of switches electrically coupled between the second output of the decoder and the set of inputs of the amplifier, respectively.
6 . The display driver of claim 5 , wherein electrically coupling the first and second outputs of the decoder during the first period comprises closing all of the first set of switches and all of the second set of switches during the first period.
7 . The display driver of claim 1 , wherein the interpolation selector is further configured to: receive a shunt control signal, wherein electrically coupling the first and second outputs of the decoder during the first period is responsive to the shunt control signal.
8 . The display driver of claim 1 , wherein a duration of the first period is programmable.
9 . The display driver of claim 1 , further comprising: a control circuit configured to adjust a duration of the first period.
10 . The display driver of claim 9 , wherein adjusting the duration of the first period is based on the first pixel data and second pixel data provided to the decoder before the first pixel data is provided to the decoder.
11 . A method, comprising: electrically coupling a first output of a decoder to a first gamma bus line of a plurality of gamma bus lines based on first pixel data provided to the decoder; electrically coupling a second output of the decoder to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data; electrically coupling, by an interpolation selector, the first and second outputs of the decoder to a set of inputs of an amplifier based on the first pixel data; electrically coupling, by the interpolation selector, the first and second outputs of the decoder during a first period of a horizontal sync period; and providing, by the amplifier, a data voltage to a display panel based on a set of input voltages at the set of inputs.
12 . The method of claim 11 , further comprising: generating a plurality of gamma voltages on the plurality of gamma bus lines.
13 . The method of claim 11 , further comprising: electrically coupling, by the interpolation selector, respective inputs of the amplifier to the first output or the second output of the decoder during a second period of the horizontal sync period, the second period following the first period.
14 . The method of claim 11 , further comprising: electrically coupling, by the interpolation selector, the first output of the decoder to the set of inputs of the amplifier via a first set of respective switches; and electrically coupling, by the interpolation selector, the second output of the decoder to the set of inputs of the amplifier via a second set of respective switches.
15 . The method of claim 14 , wherein electrically coupling the first and second outputs of the decoder during the first period comprises: closing, by the interpolation selector, all of the first set of switches and all of the second set of switches during the first period.
16 . The method of claim 11 , further comprising: receiving, by the interpolation selector, a shunt control signal, wherein electrically coupling the first and second outputs of the decoder during the first period is responsive to the shunt control signal.
17 . The method of claim 11 , wherein a duration of the first period is programmable.
18 . A display device, comprising: a display panel; and a display driver comprising: a decoder, wherein the decoder is configured to: electrically couple a first output of the decoder to a first gamma bus line of a plurality of gamma bus lines based on first pixel data provided to the decoder; and electrically couple a second output of the decoder to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data; an amplifier comprising a set of inputs and configured to provide a data voltage to the display panel based on a set of input voltages at the set of inputs; and an interpolation selector configured to: electrically couple the first and second outputs of the decoder to the set of inputs of the amplifier based on the first pixel data; and electrically couple the first and second outputs of the decoder during a first period of a horizontal sync period.
19 . The display device of claim 18 , wherein the interpolation selector is further configured to: electrically couple respective inputs of the amplifier to the first output or the second output of the decoder during a second period of the horizontal sync period, the second period following the first period.
20 . The display device of claim 18 , wherein the interpolation selector comprises: a first set of switches electrically coupled between the first output of the decoder and the set of inputs of the amplifier, respectively; and a second set of switches electrically coupled between the second output of the decoder and the set of inputs of the amplifier, respectively, wherein electrically coupling the first and second outputs of the decoder during the first period comprises closing all of the first set of switches and all of the second set of switches during the first period.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/472,068, filed on Sep. 21, 2023, which is incorporated by reference herein in its entirety. TECHNICAL FIELD This disclosure relates generally to devices and methods for driving display panels, more particularly, to slew rate enhancement at source amplifier inputs. BACKGROUND A display driver of a panel display device, such as a liquid crystal display (LCD) device, an organic light emitting diode (OLED) display device, and a micro light emitting diode (μLED) display device, may use source amplifiers to drive source lines of the display panel. In a typical implementation, the source amplifiers may each be configured to receive one or more gamma voltages selected by a decoder based on pixel data and generate a data voltage corresponding to the pixel data from the received one or more gamma voltages. The data voltages generated by the source amplifiers may be output to source lines of the display panel and then provided to selected pixels of the display panel to update or program the pixels. Due to recent increases in the display resolution and the frame rate of panel display devices, settling time reduction can be an issue with source amplifiers. The settling time referred to herein is the time required for an output to reach and remain within a given error band following some input stimulus. Reducing the settling time of source amplifiers may enhance the speed of operation of the display driver, and therefore source amplifiers may be designed to reduce the settling time. SUMMARY This summary is provided to introduce a selection of concepts in a simplified form that are further described below. This summary is not intended to necessarily identify key features or essential features of the present disclosure. The present disclosure may include the following various aspects and embodiments. In an exemplary embodiment, the present disclosure provides a display driver that includes a plurality of gamma bus lines on which a plurality of gamma voltages are generated and a drive leg configured to receive first pixel data and the plurality of gamma voltages. The drive leg includes a decoder, a source amplifier, and a source interpolation selector. The decoder has first and second outputs and is configured to electrically connect the first output to a first gamma bus line of the plurality of gamma bus lines based on the first pixel data, and electrically connect the second output to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data. The source amplifier has a set of inputs and is configured to provide a data voltage to a display panel based on a set of input voltages at the set of inputs. The source interpolation selector is configured to provide, based on the first pixel data, electrical connections between the first and second outputs of the decoder and the set of inputs of the source amplifier. The source interpolation selector is further configured to electrically connect the first and second outputs of the decoder during a first period of a horizontal sync period. In another exemplary embodiment, the present disclosure provides a display device that includes a display panel and a display driver. The display driver includes a plurality of gamma bus lines on which a plurality of gamma voltages are generated, respectively, and a drive leg configured to receive first pixel data and the plurality of gamma voltages. The drive leg includes a decoder, a source amplifier, and a source interpolation selector. The decoder has first and second outputs and is configured to electrically connect the first output to a first gamma bus line of the plurality of gamma bus lines based on the first pixel data, and electrically connect the second output to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data. The source amplifier has a set of inputs and is configured to provide a data voltage to the display panel based on a set of input voltages at the set of inputs. The source interpolation selector is configured to provide, based on the first pixel data, electrical connections between the first and second outputs of the decoder and the set of inputs of the source amplifier. The source interpolation selector is further configured to electrically connect the first output and second output of the decoder during a first period of a horizontal sync period. In yet another exemplary embodiment, the present disclosure provides a method. The method includes generating a plurality of gamma voltages on a plurality of gamma bus lines, respectively. The method further includes electrically connecting a first output of a decoder to a first gamma bus line of the plurality of gamma bus lines based on first pixel data provided to the decoder, and electrically connecting a second output of the decoder to a second gamma bus line of the plurality of gamma bus lines ba