US-12620336-B2 - Gamma voltage generation circuit and display device including the same

US12620336B2US 12620336 B2US12620336 B2US 12620336B2US-12620336-B2

Abstract

A gamma voltage generating circuit includes a plurality of tap nodes, a plurality of resistor strings connected between two tap nodes of the plurality of tap nodes, and a plurality of gamma buffers configured to generate a plurality of tap gamma voltages to output to the plurality of tap nodes, based on voltage division results of the plurality of resistor strings, wherein each of the plurality of resistor strings includes a first connection portion coupled to a tap gamma output of a first gray level and a second connection portion coupled to a tap gamma output of a second gray level which is lower than the first gray level, and the second connection portions of the plurality of resistor strings are distributed and connected to output terminals of two or more gamma buffers.

Inventors

Hyun Woo Kim
Beom Jin KIM
Hong Ju LEE

Assignees

LG DISPLAY CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20240730
Priority Date: 20231222

Claims (14)

1 . A gamma voltage generating circuit, comprising: a plurality of tap nodes; a plurality of resistor strings connected between two tap nodes of the plurality of tap nodes; and a plurality of gamma buffers configured to generate a plurality of tap gamma voltages to output to the plurality of tap nodes, based on voltage division results by the plurality of resistor strings, wherein each of the plurality of resistor strings comprises a first connection portion coupled to a tap gamma output of a first gray level and a second connection portion coupled to a tap gamma output of a second gray level which is lower than the first gray level, and wherein the second connection portions of the plurality of resistor strings are distributed and connected to output terminals of two or more gamma buffers.
2 . The gamma voltage generating circuit of claim 1 , wherein the plurality of tap gamma voltages comprises a tap gamma voltage of a highest gray level, a tap gamma voltage of a lowest gray level, and tap gamma voltages of other gray levels between the highest gray level and the lowest gray level, wherein the tap gamma voltages of the other gray levels comprise a tap gamma voltage of a second-high gray level, a tap gamma voltage of a second-low gray level, and tap gamma voltages of middle gray levels between the second-high gray level and the second-low gray level, and wherein, in a charging order of the plurality of tap gamma voltages on the plurality of tap nodes, the tap gamma voltage of the highest gray level and the tap gamma voltage of the lowest gray level are first in order, and at least one of the tap gamma voltages of the middle gray levels is latest in order.
3 . The gamma voltage generating circuit of claim 2 , wherein a number of resistor strings is equal to a number of tap gamma voltages of the other gray levels.
4 . The gamma voltage generating circuit of claim 3 , wherein an input terminal of each of a plurality of other gamma buffers generating the tap gamma voltages of the other gray levels is connected to one resistor string through a multiplexer.
5 . The gamma voltage generating circuit of claim 2 , wherein a number of resistor strings is less than a number of tap gamma voltages of the other gray levels.
6 . The gamma voltage generating circuit of claim 5 , wherein a plurality of other gamma buffers generating the tap gamma voltages of the other gray levels is connected to one resistor string through multiplexers in common.
7 . The gamma voltage generating circuit of claim 1 , wherein currents flowing in the plurality of resistor strings do not concentrate on an output terminal of one gamma buffer and are distributed to output terminals of the two or more gamma buffers.
8 . A display apparatus, comprising: a display panel including a plurality of pixels; a gamma voltage generating circuit configured to output gamma compensation voltages including a plurality of tap gamma voltages; and a digital-to-analog converter configured to map input image data to the gamma compensation voltages to output data voltages which are to be input to the plurality of pixels, wherein the gamma voltage generating circuit comprises: a plurality of tap nodes; a plurality of resistor strings connected between two tap nodes of the plurality of tap nodes; and a plurality of gamma buffers configured to generate a plurality of tap gamma voltages to output to the plurality of tap nodes, based on voltage division results of the plurality of resistor strings, wherein each of the plurality of resistor strings comprises a first connection portion coupled to a tap gamma output of a first gray level and a second connection portion coupled to a tap gamma output of a second gray level which is lower than the first gray level, and wherein the second connection portions of the plurality of resistor strings are distributed and connected to output terminals of two or more gamma buffers.
9 . The display apparatus of claim 8 , wherein the plurality of tap gamma voltages comprises a tap gamma voltage of a highest gray level, a tap gamma voltage of a lowest gray level, and tap gamma voltages of other gray levels between the highest gray level and the lowest gray level, wherein the tap gamma voltages of the other gray levels comprise a tap gamma voltage of a second-high gray level, a tap gamma voltage of a second-low gray level, and tap gamma voltages of middle gray levels between the second-high gray level and the second-low gray level, and wherein, in a charging order of the plurality of tap gamma voltages on the plurality of tap nodes, the tap gamma voltage of the highest gray level and the tap gamma voltage of the lowest gray level are first in order, and at least one of the tap gamma voltages of the middle gray levels is latest in order.
10 . The display apparatus of claim 9 , wherein a number of resistor strings is equal to a number of tap gamma voltages of the other gray levels.
11 . The display apparatus of claim 10 , wherein an input terminal of each of a plurality of other gamma buffers generating the tap gamma voltages of the other gray levels is connected to one resistor string through a multiplexer.
12 . The display apparatus of claim 9 , wherein a number of resistor strings is less than a number of tap gamma voltages of the other gray levels.
13 . The display apparatus of claim 12 , wherein a plurality of other gamma buffers generating the tap gamma voltages of the other gray levels is connected to one resistor string through multiplexers in common.
14 . The display apparatus of claim 8 , wherein currents flowing in the plurality of resistor strings do not concentrate on an output terminal of one gamma buffer and are distributed to output terminals of the two or more gamma buffers.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of the Korean Patent Application No. 10-2023-0189480 filed on Dec. 22, 2023, which is hereby incorporated by reference as if fully set forth herein. BACKGROUND Technical Field The present disclosure relates to a gamma voltage generating circuit and a display apparatus including the same. Description of the Related Art Display apparatuses supply data voltages to pixels having different sizes for each gray level, so as to display an input image. The data voltages are output by digital-to-analog converters, based on gamma compensation voltages generated by a gamma voltage generating circuit. In display apparatuses having a high resolution and a high frequency, because a time margin of a gamma output is small, a time for which the gamma output is settled to a target voltage should be short. To this end, a time for which the gamma output is unsettled in a transient state should be reduced, namely, an output response time of a gamma voltage generating circuit should be fast. A method of decreasing an internal load resistance level of the gamma voltage generating circuit may be considered for improving the output response time of the gamma voltage generating circuit, but there may be a problem where a specific gamma buffer is abnormally driven due to an overcurrent. For this reason, because it is difficult to decrease a load resistance level, the use of a large-capacity gamma buffer having good driving capability is needed. However, a gamma buffer having a large size causes an increase in circuit size of the gamma voltage generating circuit. BRIEF SUMMARY To overcome the aforementioned problem of the related art, the present disclosure may provide a gamma voltage generating circuit and a display apparatus including the same, which may implement a fast response time with no problem of an abnormal operation caused by an overcurrent even without an increase in size of a gamma buffer. To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a gamma voltage generating circuit includes a plurality of tap nodes, a plurality of resistor strings connected between two tap nodes of the plurality of tap nodes, and a plurality of gamma buffers configured to generate a plurality of tap gamma voltages to output to the plurality of tap nodes, based on voltage division results of the plurality of resistor strings, wherein each of the plurality of resistor strings includes a first connection portion coupled to a tap gamma output of a first gray level and a second connection portion coupled to a tap gamma output of a second gray level which is lower than the first gray level, and the second connection portions of the plurality of resistor strings are distributed and connected to output terminals of two or more gamma buffers. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings: FIG. 1 is a diagram illustrating a display apparatus according to the present embodiment; FIG. 2 is a diagram illustrating a data driving circuit of a display apparatus according to the present embodiment; FIG. 3 is a diagram showing an operation timing of the data driving circuit of FIG. 2; FIG. 4 is a diagram illustrating a gamma voltage generating circuit according to a comparative example; FIG. 5 is a diagram illustrating a flow of an internal current when an internal resistance load is reduced, in the gamma voltage generating circuit according to a comparative example; FIGS. 6 and 7 are diagrams showing a gamma voltage determination order and an output settling time based thereon in the gamma voltage generating circuit according to a comparative example; FIGS. 8 and 9 are diagrams illustrating a gamma voltage generating circuit according to a first embodiment; FIG. 10 is a diagram illustrating a flow of an internal current when an internal resistance load is reduced, in the gamma voltage generating circuit according to the first embodiment; FIGS. 11 and 12 are diagrams showing a gamma voltage determination order and an output settling time based thereon in the gamma voltage generating circuit according to the first embodiment; FIG. 13 is a diagram illustrating an example where an output settling time is more reduced in the first embodiment than the comparative example; FIG. 14 is a diagram illustrating a gamma voltage generating circuit according to a second embodiment; FIG. 15 is a diagram illustrating a gamma voltage generating circuit according to a third embodiment; and FIG. 16 is a diagram illustrating a gamma voltage generating circuit according to a fourth embodiment. DETAILED DESCRIP