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US-12620353-B2 - Display panel

US12620353B2US 12620353 B2US12620353 B2US 12620353B2US-12620353-B2

Abstract

Provided is a display panel. The display panel includes a pixel driving circuit including a drive transistor, a data write module, a light emission control module, a threshold compensation module and a bias adjustment module. The control terminal of the drive transistor is connected to the first node. The first terminal of the drive transistor is connected to a third node. The second terminal of the drive transistor is connected to a second node. The light emission control module is connected in series with the drive transistor and connected in series with a light-emitting element. The threshold compensation module is connected in series between the control terminal of the drive transistor and the second terminal of the drive transistor. The first terminal of the bias adjustment module is connected to a bias signal terminal. The second terminal is connected to the second terminal of the drive transistor.

Inventors

  • Jieliang LI
  • Gaojun Huang

Assignees

  • XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.

Dates

Publication Date
20260505
Application Date
20231127
Priority Date
20201015

Claims (6)

  1. 1 . A display panel, comprising a pixel driving circuit, wherein the pixel driving circuit comprises: a drive transistor, a second transistor, a fourth transistor and a fifth transistor, a first transistor transistor, and a third transistor, wherein a control terminal of the drive transistor is connected to a first node, a first terminal of the drive transistor is connected to a third node, and a second terminal of the drive transistor is connected to a second node; the second transistor is configured to provide a data signal to the drive transistor during a data write stage; the fourth transistor and the fifth transistor are connected in series with the drive transistor and a light-emitting element respectively and is configured to control whether a drive current flows through the light-emitting element; the first transistor is connected in series between the control terminal of the drive transistor and the second terminal of the drive transistor; a first terminal of the third transistor is connected to a bias signal terminal, a second terminal of the third transistor is connected to the second terminal of the drive transistor, and a control terminal of the third transistor is connected to a first control signal terminal; during a second period, the third transistor directly connected to the second node is at an on-state; time of the second period is 12H; and just after the second period, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are off for time of 4H.
  2. 2 . The display panel of claim 1 , wherein a high level is written to the second node during at least part of the second period.
  3. 3 . The display panel according to claim 2 , wherein during the second period, the high level written has a range from 4V to 10V.
  4. 4 . The display panel of claim 1 , further comprising a second bias adjustment stage after the data write stage, wherein a duration of the second bias adjustment stage is shorter than a duration of the second period.
  5. 5 . The display panel of claim 1 , further comprising a sixth transistor, wherein the control terminal of the drive transistor and a first terminal of the first transistor are electrically connected to the first node and the second terminal of the drive transistor and a second terminal of the first transistor are electrically connected to the second node; a control terminal of the second transistor is electrically connected to a second control signal terminal, a first terminal of the second transistor is electrically connected to a data signal terminal and a second terminal of the second transistor and the first terminal of the drive transistor are electrically connected to the third node; a first terminal of the fourth transistor is electrically connected to a first level signal input terminal, a second terminal of the fourth transistor and the first terminal of the drive transistor are electrically connected to the third node, a first terminal of the fifth transistor is electrically connected to the second node, and a second terminal of the fifth transistor is electrically connected to the light-emitting element; and a first terminal of the sixth transistor is electrically connected to a reset signal terminal and a second terminal of the sixth transistor is electrically connected to the light-emitting element.
  6. 6 . The display panel of claim 5 , wherein an active layer of the drive transistor, an active layer of the second transistor, an active layer of the fourth transistor or the fifth transistor, and an active layer of the third transistor each comprise a low-temperature polycrystalline silicon material; a channel width-to-length ratio of the first transistor is greater than a channel width-to-length ratio of the drive transistor, a channel width-to-length ratio of the second transistor, a channel width-to-length ratio of the fourth transistor or the fifth transistor, and a channel width-to-length ratio of the third transistor; and an active layer of the first transistor comprises an oxide semiconductor.

Description

This application is a continuation of U.S. patent application Ser. No. 17/858,347 filed on Jul. 6, 2022, which is a continuation of U.S. patent application Ser. No. 17/164,019 filed on Feb. 1, 2021, which claims priority to Chinese Patent Application No. 202011104618.4 filed on Oct. 15, 2020, and the disclosures of which are incorporated herein by reference in their entireties. TECHNICAL FIELD The present disclosure relates to the field of display panels and, in particular, to a display panel. BACKGROUND An organic light-emitting display device has advantages such as self-luminescence, a low drive voltage, high luminescence efficiency, a fast response speed, lightness and thinness, and a high contrast ratio and is considered to be one of the most promising display devices of the next generation. A pixel in the organic light-emitting display device includes a pixel driving circuit. The drive transistor in the pixel driving circuit may generate a drive current, and a light-emitting element emits light in response to the drive current. However, factors such as operational techniques and device aging may lead to transistor's threshold value drift, affecting the drive current. Moreover, the hysteresis effect at the times of image switching between high grayscales and low grayscales may lead to an afterimage and a non-uniform brightness of images in the first several frames after the image switching, which causes user's eyes to perceive flickers. SUMMARY Embodiments of the present disclosure provide a display panel including a pixel driving circuit. The pixel driving circuit includes a drive transistor, a data write module, a light emission control module, a threshold compensation module and a bias adjustment module. A control terminal of the drive transistor is connected to a first node, a first terminal of the drive transistor is connected to a third node, and a second terminal of the drive transistor is connected to a second node. The data write module is configured to provide a data signal to the drive transistor. The light emission control module is connected in series with the drive transistor and a light-emitting element respectively and is configured to control whether a drive current flows through the light-emitting element. The threshold compensation module is connected in series between the control terminal of the drive transistor and the second terminal of the drive transistor and configured to detect and self-compensate for a threshold voltage deviation of the drive transistor. A first terminal of the bias adjustment module is connected to a bias signal terminal, a second terminal of the bias adjustment module is connected to the second terminal of the drive transistor, a control terminal of the bias adjustment module is connected to a first control signal terminal, and the bias adjustment module is configured to adjust, under control of a first control signal inputted through the first control signal terminal and a bias signal inputted through the bias signal terminal, a bias state of the drive transistor. During a first period, the threshold compensation module and another transistor are turned on simultaneously, and the first node and the second node are electrically connected. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. FIG. 2 is a schematic circuit diagram of another pixel driving circuit according to some embodiments of the present disclosure. FIG. 3 is a schematic circuit diagram of another pixel driving circuit according to some embodiments of the present disclosure. FIG. 4 is a schematic circuit diagram of another pixel driving circuit according to some embodiments of the present disclosure. FIG. 5 is a schematic circuit diagram of another pixel driving circuit according to some embodiments of the present disclosure. FIG. 6 is a schematic circuit diagram of another pixel driving circuit according to some embodiments of the present disclosure. FIG. 7 is a flowchart of a driving method of a display panel according to some embodiments of the present disclosure. FIG. 8 is a drive timing diagram of a display panel according to some embodiments of the present disclosure. FIG. 9 is a flowchart of another driving method of a display panel according to some embodiments of the present disclosure. FIG. 10 is another drive timing diagram of a display panel according to some embodiments of the present disclosure. FIG. 11 is a flowchart of another driving method of a display panel according to some embodiments of the present disclosure. FIG. 12 is a flowchart of another driving method of a display panel according to some embodiments of the present disclosure. FIG. 13 is a flowchart of another driving method of a display panel according to some embodiments of the present disclosure. FIG. 14 is another drive timing diagram of a display panel according to some embodiments of the present disclosure. FIG