US-12620355-B2 - Pixel and display apparatus

Abstract

A pixel includes a first transistor to output a current supplied to a light-emitting device, a second transistor electrically connected between a gate of the first transistor and a first terminal of the first transistor, a third transistor electrically connected between the first voltage line and a second terminal of the first transistor, a fourth transistor electrically connected between the first terminal of the first transistor and the light-emitting device, and a fifth transistor configured to supply a bias voltage to the second terminal of the first transistor. A gate-on voltage may be supplied to a gate of the fifth transistor during a portion of a period during which a gate-off voltage may be supplied to a gate of the third transistor and a gate of the fourth transistor.

Inventors

• Jaewoo Lee
• Taeho Kim
• Sungeun Lee
• Seungjun LEE
• Sangmin JEON

Assignees

• SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date

20260505

Application Date

20240927

Priority Date

20231004

Claims (19)

1. 1 . A pixel comprising: a light-emitting device; a first transistor electrically connected between a first voltage line and the light-emitting device and configured to control a current supplied to the light-emitting device; a second transistor electrically connected between a first node electrically connected to a gate of the first transistor and a second node electrically connected to a first terminal of the first transistor; a third transistor electrically connected between the first voltage line and a third node electrically connected to a second terminal of the first transistor; a fourth transistor electrically connected between the second node and the light-emitting device; and a fifth transistor configured to supply a bias voltage to the third node, wherein a gate driving circuit is configured to supply a gate-on voltage of a first level to a gate of the fifth transistor during at least a portion of a period during which the gate driving circuit supplies a gate-off voltage of a second level to a gate of the third transistor and a gate of the fourth transistor, wherein a frame includes a first scan period during which a data driving circuit is configured to supply a data signal and the light-emitting device is configured to emit light with a brightness corresponding to the data signal, and wherein the gate driving circuit is configured to supply the gate-on voltage to a gate of the second transistor and to the gate of the fifth transistor such that an on and off pattern of the second transistor is the same as an on and off pattern of the fifth transistor during the first scan period.
2. 2 . The pixel of claim 1 , wherein the frame includes a second scan period during which the data signal supplied during the first scan period is maintained and light is emitted with the brightness corresponding to the data signal, and the fifth transistor is configured to supply a first bias voltage to the third node in response to the gate-on voltage being supplied to the gate of the fifth transistor during the first scan period, and supply a second bias voltage to the third node in response to the gate-on voltage being supplied to the gate of the fifth transistor during the second scan period.
3. 3 . The pixel of claim 2 , wherein the second bias voltage is higher than the first bias voltage.
4. 4 . The pixel of claim 2 , wherein the first scan period includes a first period during which the gate driving circuit is configured to supply the gate-on voltage to each of the gate of the second transistor and the gate of the fifth transistor within the period during which the gate driving circuit supplies the gate-off voltage of the second level to the gate of the third transistor and the gate of the fourth transistor, and the second scan period includes a second period during which the gate driving circuit is configured to supply the gate-off voltage to the gate of the second transistor and supply the gate-on voltage to the gate of the fifth transistor within the period during which the gate driving circuit supplies the gate-off voltage of the second level to the gate of the third transistor and the gate of the fourth transistor.
5. 5 . The pixel of claim 4 , wherein the gate of the third transistor and the gate of the fourth transistor are electrically connected to a first gate line, and the gate of the fifth transistor is electrically connected to a second gate line.
6. 6 . The pixel of claim 5 , further comprising: a sixth transistor electrically connected between a pixel electrode of the light-emitting device and a second voltage line, and wherein a gate of the sixth transistor is electrically connected to the second gate line.
7. 7 . The pixel of claim 6 , further comprising: a first capacitor electrically connected between the first voltage line and a fourth node; a second capacitor electrically connected between the fourth node and the first node; a seventh transistor electrically connected between a data line and the fourth node; an eighth transistor electrically connected between the fourth node and a third voltage line; and a ninth transistor electrically connected between the first node and a fourth voltage line.
8. 8 . The pixel of claim 7 , wherein the fifth transistor is electrically connected between the third node and the third voltage line.
9. 9 . The pixel of claim 8 , wherein a gate of the seventh transistor is electrically connected to a third gate line, the gate of the second transistor and a gate of the eighth transistor are electrically connected to a fourth gate line, and a gate of the ninth transistor is electrically connected to a fifth gate line.
10. 10 . A display apparatus comprising: a plurality of pixels; and a gate driving circuit configured to supply a plurality of gate signals to the plurality of pixels, wherein each of the plurality of pixels comprises: a light-emitting device; a first transistor electrically connected between a first voltage line and the light-emitting device and configured to control a current supplied to the light-emitting device; a second transistor electrically connected between a first node electrically connected to a gate of the first transistor and a second node electrically connected to a first terminal of the first transistor; a third transistor electrically connected between the first voltage line and a third node electrically connected to a second terminal of the first transistor; a fourth transistor electrically connected between the second node and the light-emitting device; and a fifth transistor configured to supply a bias voltage to the third node, wherein a gate of the third transistor and a gate of the fourth transistor are electrically connected to a first gate line configured to supply a first gate signal, wherein a gate of the fifth transistor is electrically connected to a second gate line configured to supply a second gate signal, wherein a gate of the second transistor is electrically connected to a third gate line configured to supply a third gate signal, wherein a frame includes a first scan period during which a data driving circuit is configured to supply a data signal and the light-emitting device is configured to emit light with a brightness corresponding to the data signal, and wherein the gate driving circuit is configured to supply a gate-on voltage to the third gate line of the second transistor and to the second gate line of the fifth transistor such that an on and off pattern of the second transistor is the same as an on and off pattern of the fifth transistor during the first scan period.
11. 11 . The display apparatus of claim 10 , wherein each of the plurality of pixels further comprises: a first capacitor electrically connected between the first voltage line and a fourth node; a second capacitor electrically connected between the fourth node and the first node; a sixth transistor electrically connected between a data line and the fourth node; a seventh transistor electrically connected between the fourth node and a second voltage line; an eighth transistor electrically connected between the first node and a third voltage line; and a ninth transistor electrically connected between a pixel electrode of the light-emitting device and a fourth voltage line.
12. 12 . The display apparatus of claim 11 , wherein the fifth transistor is electrically connected between the third node and the second voltage line.
13. 13 . The display apparatus of claim 12 , wherein a gate of the ninth transistor is electrically connected to the second gate line, a gate of the seventh transistor is electrically connected to the third gate line, a gate of the sixth transistor is electrically connected to a fourth gate line configured to supply a fourth gate signal, and a gate of the eighth transistor is electrically connected to a fifth gate line configured to supply a fifth gate signal.
14. 14 . The display apparatus of claim 13 , wherein the fifth transistor is configured to supply a first bias voltage to the third node during the first scan period.
15. 15 . The display apparatus of claim 14 , wherein the frame further includes at least one second scan period subsequent to the first scan period, wherein, during the at least one second scan period, the data signal supplied during the first scan period is maintained and the light-emitting device is configured to emit light with a brightness corresponding to the data signal, and the fifth transistor is configured to supply a second bias voltage to the third node during the at least one second scan period.
16. 16 . The display apparatus of claim 15 , wherein the second bias voltage is higher than the first bias voltage.
17. 17 . The display apparatus of claim 15 , wherein the first scan period and the at least one second scan period include a non-emission period and an emission period, respectively, and the gate driving circuit is configured to supply: a first gate signal of a gate-off voltage to the first gate line during a non-emission period of each of the first scan period and the at least one second scan period, a second gate signal of a gate-on voltage to the second gate line and a third gate signal of a gate-on voltage to the third gate line during a first period of the non-emission period of the first scan period, and the second gate signal of a gate-on voltage to the second gate line and the third gate signal of a gate-off voltage to the third gate line during a second period of the non-emission period of the at least one second scan period.
18. 18 . The display apparatus of claim 17 , wherein the gate driving circuit is configured to supply a fourth gate signal of a gate-on voltage to the fourth gate line during a write period between the first period of the first scan period and the emission period of the first scan period.
19. 19 . The display apparatus of claim 17 , wherein the gate driving circuit is configured to supply a fifth gate signal of a gate-on voltage to the fifth gate line prior to the first period of the non-emission period of the first scan period.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2023-0132076 filed on Oct. 4, 2023 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. BACKGROUND 1. Technical Field One or more embodiments relate to a pixel and a display apparatus including the same. 2. Description of the Related Art Applications of display apparatuses have recently diversified. Moreover, since display apparatuses have become thinner and lighter, their range of use has increased. Given that display apparatuses may be utilized in various ways, various methods may be used to design the shapes of display apparatuses, and functions that may be electrically connected or linked to display apparatuses are increasing. SUMMARY One or more embodiments include a display apparatus having an improved display quality. However, aspects of embodiments may not be limited thereto, and the above characteristics do not limit the scope of embodiments according to the disclosure. Additional aspects will be set forth in portion in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure. According to one or more embodiments, a pixel may include a light-emitting device, a first transistor electrically connected between a first voltage line and the light-emitting device and configured to control a current supplied to the light-emitting device, a second transistor electrically between a first node electrically connected to a gate of the first transistor and a second node electrically connected to a first terminal of the first transistor, a third transistor electrically connected between the first voltage line and a third node electrically connected to a second terminal of the first transistor, a fourth transistor electrically connected between the second node and the light-emitting device, and a fifth transistor configured to supply a bias voltage to the third node. A gate-on voltage of a first level may be supplied to a gate of the fifth transistor during at least a portion of a period during which a gate-off voltage of a second level may be supplied to a gate of the third transistor and a gate of the fourth transistor. The gate-on voltage may be supplied to a gate of the second transistor while the gate-on voltage may be supplied to the gate of the fifth transistor. A frame may include a first scan period during which a data signal may be supplied and light may be emitted with a brightness corresponding to the data signal, and a second scan period during which the data signal supplied during the first scan period may be maintained and light may be emitted with the brightness corresponding to the data signal. The fifth transistor may supply a first bias voltage to the third node in case that the gate-on voltage may be supplied to the gate of the fifth transistor during the first scan period, and may supply a second bias voltage to the third node in case that the gate-on voltage may be supplied to the gate of the fifth transistor during the second scan period. The second bias voltage may be higher than the first bias voltage. The first scan period may include a first period during which the gate-on voltage may be supplied to each of a gate of the second transistor and the gate of the fifth transistor within the period during which the gate-off voltage of the second level may be supplied to the gate of the third transistor and the gate of the fourth transistor. The second scan period may include a second period during which the gate-off voltage may be supplied to the gate of the second transistor and the gate-on voltage may be supplied to the gate of the fifth transistor within the period during which the gate-off voltage of the second level may be supplied to the gate of the third transistor and the gate of the fourth transistor. The gate of the third transistor and the gate of the fourth transistor may be electrically connected to a first gate line, and the gate of the fifth transistor may be electrically connected to a second gate line. The pixel may further include a sixth transistor electrically connected between a pixel electrode of the light-emitting device and a second voltage line, and a gate of the sixth transistor may be electrically connected to the second gate line. The pixel may further include a first capacitor electrically connected between the first voltage line and a fourth node, a second capacitor electrically connected between the fourth node and the first node, a seventh transistor electrically connected between a data line and the fourth node, an eighth transistor electrically connected between the fourth node and a third voltage line, and a ninth transistor electrically connected between the first node and a fourth voltage line. The fifth transistor may be electrically connected between the third node