US-12620362-B2 - Driving circuit

Abstract

A stage of a driving circuit includes seventh and eighth transistors electrically connected between a first terminal for receiving a first voltage and a second terminal for receiving a second voltage that is lower than the first voltage, ninth and tenth transistors electrically connected between the first and second terminals, and a fourth transistor including a gate electrically connected to a first node configured to receive the start signal and a back gate electrically connected to a third node, and electrically connected between the second terminal and a second node to which a gate of the eighth transistor is electrically connected, a fifth transistor electrically connected between the first node and the third node, and including a gate electrically connected to the second terminal, and a second capacitor electrically connected to the third node and to a second output node between the ninth and tenth transistors.

Inventors

• Junhyun Park
• Youngwan Seo
• Soil YOON

Assignees

• SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date

20260505

Application Date

20250110

Priority Date

20240226

Claims (19)

1. 1 . A driving circuit comprising stages, the stages comprising: a first output circuit configured to output an output signal, and comprising a seventh transistor and an eighth transistor electrically connected between a first voltage input terminal for receiving a first voltage and a second voltage input terminal for receiving a second voltage that is lower than the first voltage; a second output circuit configured to output a carry signal, and comprising a ninth transistor and a tenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal; and a control circuit electrically connected to the first output circuit, to the second output circuit, and to an input terminal configured to receive a start signal, and comprising: a fourth transistor comprising a gate electrically connected to a first node configured to receive the start signal and a back gate electrically connected to a third node, and electrically connected between the second voltage input terminal and a second node to which a gate of the eighth transistor is electrically connected; a fifth transistor electrically connected between the first node and the third node, and comprising a gate electrically connected to the second voltage input terminal; and a second capacitor electrically connected to the third node and to a second output node between the ninth transistor and the tenth transistor.
2. 2 . The driving circuit of claim 1 , wherein, when a voltage of the first node is at a high level, a voltage of the third node is at a high level that is substantially equal to the high level of the voltage of the first node, and wherein, when the voltage of the first node is at a low level, the voltage of the third node is at a low level that is lower than the low level of the voltage of the first node.
3. 3 . The driving circuit of claim 1 , wherein the fourth transistor comprises an N-channel transistor, and the fifth transistor comprises a P-channel transistor.
4. 4 . The driving circuit of claim 3 , wherein the fourth transistor comprises an oxide transistor, and the fifth transistor comprises a silicon transistor.
5. 5 . The driving circuit of claim 3 , wherein the first output circuit further comprises a sixth transistor electrically connected between the second voltage input terminal and a first output node between the seventh transistor and the eighth transistor, and comprising a gate electrically connected to the third node.
6. 6 . The driving circuit of claim 1 , wherein the control circuit further comprises: a first transistor electrically connected between the input terminal and the first node, and comprising a gate electrically connected to a first clock terminal configured to receive a first clock signal; and a second transistor electrically connected between the input terminal and the first node, and comprising a gate electrically connected to a second clock terminal configured to receive a second clock signal.
7. 7 . The driving circuit of claim 6 , wherein the second transistor further comprises a back gate electrically connected to a third terminal configured to receive a third voltage that is lower than the second voltage.
8. 8 . The driving circuit of claim 6 , wherein the second clock signal is an inverted signal of the first clock signal.
9. 9 . The driving circuit of claim 6 , wherein the control circuit further comprises a third transistor electrically connected between the first voltage input terminal and the second node, and comprising a gate electrically connected to the first node.
10. 10 . The driving circuit of claim 1 , wherein the eighth transistor comprises a back gate electrically connected to a third terminal configured to receive a third voltage that is lower than the second voltage.
11. 11 . The driving circuit of claim 1 , wherein the tenth transistor comprises a back gate electrically connected to a third terminal configured to receive a third voltage that is lower than the second voltage.
12. 12 . The driving circuit of claim 1 , further comprising a third output circuit comprising a thirteenth transistor and a fourteenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal, and configured to output a second carry signal, wherein, when the carry signal is at a high level, the second carry signal is at a low level, and wherein, when the carry signal is at a low level, the second carry signal is at a high level.
13. 13 . The driving circuit of claim 12 , wherein the control circuit further comprises: a twelfth transistor electrically connected between the second node and a fourth node, and comprising a gate electrically connected to the second voltage input terminal; and a third capacitor electrically connected to the fourth node and to a third output node between the thirteenth transistor and the fourteenth transistor, wherein the eighth transistor comprises a back gate electrically connected to the fourth node.
14. 14 . The driving circuit of claim 13 , wherein, when a voltage of the second node is at a high level, a voltage of the fourth node is at a high level that is substantially equal to the high level of the voltage of the second node, and wherein, when the voltage of the second node is at a low level, the voltage of the fourth node is at a low level that is lower than the low level of the voltage of the second node.
15. 15 . A driving circuit comprising stages, the stages comprising: a seventh transistor and an eighth transistor electrically connected between a first voltage input terminal configured to receive a first voltage and a second voltage input terminal configured to receive a second voltage that is lower than the first voltage, and configured to transmit an output signal to a first output terminal; a ninth transistor and a tenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal, and configured to transmit a carry signal to a second output terminal; a first transistor electrically connected between a first node and an input terminal configured to receive a start signal, and comprising a gate configured to receive a clock signal; a fourth transistor electrically connected between the second voltage input terminal and a second node to which a gate of the eighth transistor is electrically connected, and comprising a gate electrically connected to the first node and a back gate configured to receive an alternating current voltage; a fifth transistor electrically connected between the first node and a third node, and comprising a gate electrically connected to the second voltage input terminal; and a first capacitor electrically connected to the third node and to the second output terminal, wherein the back gate of the fourth transistor is electrically connected to the third node.
16. 16 . The driving circuit of claim 15 , wherein, when a voltage of the first node is at a high level, a voltage of the third node is at a high level that is substantially equal to the high level of the voltage of the first node, and wherein, when the voltage of the first node is at a low level, the voltage of the third node is at a low level that is lower than the low level of the voltage of the first node.
17. 17 . The driving circuit of claim 15 , further comprising a sixth transistor electrically connected between the first output terminal and the second voltage input terminal, and comprising a gate electrically connected to the third node.
18. 18 . The driving circuit of claim 15 , further comprising: a thirteenth transistor and a fourteenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal, and configured to transmit a second carry signal to a third output terminal; a twelfth transistor electrically connected between the second node and a fourth node, and comprising a gate electrically connected to the second voltage input terminal; and a third capacitor electrically connected to the fourth node and to the third output terminal, wherein the eighth transistor comprises a back gate electrically connected to the fourth node.
19. 19 . The driving circuit of claim 18 , wherein, when a voltage of the second node is at a high level, a voltage of the fourth node is at a high level that is substantially equal to the high level of the voltage of the second node, and wherein, when the voltage of the second node is at a low level, the voltage of the fourth node is at a low level that is lower than the low level of the voltage of the second node.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority to, and the benefit of, Korean Patent Application No. 10-2024-0027502, filed on Feb. 26, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field One or more embodiments relate to a driving circuit for outputting a gate signal, and a display apparatus including the driving circuit. 2. Description of the Related Art A display apparatus includes a pixel area including a plurality of pixels, a gate-driving circuit, a data-driving circuit, a controller, and/or the like. The gate-driving circuit includes stages connected to gate lines, and the stages respectively supply gate signals to the gate lines connected thereto in response to signals from the controller. SUMMARY One or more embodiments include a driving circuit capable of stably outputting a gate signal at low power, and a display apparatus including the driving circuit. Technical solutions to be achieved by the disclosure are not limited to the technical solutions mentioned above, and other technical solutions not mentioned above may be clearly understood from the description of the disclosure by those of ordinary skill in the art. Additional aspects will be set forth in part in the description that follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure. According to one or more embodiments, a driving circuit includes stages, the stages including a first output circuit configured to output an output signal, and including a seventh transistor and an eighth transistor electrically connected between a first voltage input terminal for receiving a first voltage and a second voltage input terminal for receiving a second voltage that is lower than the first voltage, a second output circuit configured to output a carry signal, and including a ninth transistor and a tenth transistor electrically connected between the first voltage input terminal and the second voltage input terminal, and a control circuit electrically connected to the first output circuit, to the second output circuit, and to an input terminal configured to receive a start signal, and including a fourth transistor including a gate electrically connected to a first node configured to receive the start signal and a back gate electrically connected to a third node, and electrically connected between the second voltage input terminal and a second node to which a gate of the eighth transistor is electrically connected, a fifth transistor electrically connected between the first node and the third node, and including a gate electrically connected to the second voltage input terminal, and a second capacitor electrically connected to the third node and to a second output node between the ninth transistor and the tenth transistor. When a voltage of the first node is at a high level, a voltage of the third node may be at a high level that is substantially equal to the high level of the voltage of the first node, wherein, when the voltage of the first node is at a low level, the voltage of the third node is at a low level that is lower than the low level of the voltage of the first node. The fourth transistor may include an N-channel transistor, and the fifth transistor may include a P-channel transistor. The fourth transistor may include an oxide transistor, and the fifth transistor may include a silicon transistor. The first output circuit may further include a sixth transistor electrically connected between the second voltage input terminal and a first output node between the seventh transistor and the eighth transistor, and including a gate electrically connected to the third node. The control circuit may further include a first transistor electrically connected between the input terminal and the first node, and including a gate electrically connected to a first clock terminal configured to receive a first clock signal, and a second transistor electrically connected between the input terminal and the first node, and including a gate electrically connected to a second clock terminal configured to receive a second clock signal. The second transistor may further include a back gate electrically connected to a third terminal configured to receive a third voltage that is lower than the second voltage. The second clock signal may be an inverted signal of the first clock signal. The control circuit may further include a third transistor electrically connected between the first voltage input terminal and the second node, and including a gate electrically connected to the first node. The eighth transistor may include a back gate electrically connected to a third terminal configured to receive a third voltage that is lower than the second voltage. The tenth transistor may include a back gate electrically connected to a third terminal configured to receive a third vo