US-12620363-B2 - Driving circuit

Abstract

A gate driving circuit includes stages, where each stage of the gate driving circuit includes a second transistor connected between a first node and a second node and which includes a first gate connected to a second terminal through which a first voltage is supplied and a second gate connected to a third terminal through which a second voltage is supplied, a fourth transistor connected between the second terminal and an output terminal and which includes a first gate connected to the second node and a second gate connected to the third node, a first capacitor connected between the second node and the output terminal and a second capacitor connected between the third node and the output terminal.

Inventors

• Kyunghoon Kim
• Kyonghwan OH
• JoonDong Kim

Assignees

• SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date

20260505

Application Date

20250117

Priority Date

20240313

Claims (20)

1. 1 . A driving circuit comprising a plurality of stages, wherein each of the plurality of stages comprises: a first transistor connected between a first node and a first terminal through which a start signal is input and comprising a gate connected to a clock terminal through which a clock signal is input; a second transistor connected between the first node and a second node and comprising a first gate connected to a second terminal through which a first voltage is supplied and a second gate connected to a third terminal through which a second voltage is supplied; a third transistor connected between the first node and a third node and comprising a gate connected to the third terminal; a fourth transistor connected between the second terminal and an output terminal and comprising a first gate connected to the second node and a second gate connected to the third node; a fifth transistor connected between the third terminal and the output terminal and comprising a gate connected to the third node; a first capacitor connected between the second node and the output terminal; and a second capacitor connected between the third node and the output terminal, wherein the first voltage is a high-level voltage and the second voltage is a low-level voltage.
2. 2 . The driving circuit of claim 1 , further comprising: a sixth transistor connected between the first node and the third terminal and comprising a gate connected to a fourth terminal which is configured to supply a reset signal; and a third capacitor connected between the first node and the second terminal.
3. 3 . The driving circuit of claim 1 , wherein the first transistor, the third transistor, and the fifth transistor are P-type transistors, and wherein the second transistor and the fourth transistor are N-type transistors.
4. 4 . The driving circuit of claim 2 , wherein the start signal comprises an external signal or an output signal which is output by a previous stage.
5. 5 . The driving circuit of claim 2 , further comprising a seventh transistor connected between the output terminal and the fifth transistor and which comprises a gate connected to the third node.
6. 6 . The driving circuit of claim 1 , wherein the clock signal alternates between a first voltage level and a second voltage level, and wherein the first voltage level is a high-level voltage level and the second voltage level is a low-level voltage level.
7. 7 . The driving circuit of claim 6 , wherein a clock signal input to a clock terminal of even-numbered stages among the plurality of stages is shifted by a half period from a clock signal input to a clock terminal of odd-numbered stages.
8. 8 . The driving circuit of claim 7 , wherein, in a first section in which the start signal of the first voltage level is input and in which the clock signal of the second voltage level is input, a voltage of the first node and the third node is at the first voltage level and a voltage of the second node is at a third voltage level, wherein the third voltage level is higher than the first voltage level, and an output signal of the first voltage level is output from the output terminal by the fourth transistor when the fourth transistor is turned-on.
9. 9 . The driving circuit of claim 8 , wherein, in a second section which follows the first section and in which the start signal of the first voltage level is input and in which the clock signal of the first voltage level is input, a voltage of the first node and the third node is at the first voltage level and a voltage of the second node is at the third voltage level, and an output signal of the first voltage level is output from the output terminal by the fourth transistor when the fourth transistor is turned-on.
10. 10 . The driving circuit of claim 9 , wherein, in a third section which follows the second section and in which the start signal of the second voltage level is input and in which the clock signal of the first voltage level is input, a voltage of the first node and the second node is at the first voltage level and a voltage of the third node is at the third voltage level, and an output signal of the first voltage level is output from the output terminal by the fourth transistor when the fourth transistor is turned-on.
11. 11 . The driving circuit of claim 10 , wherein, in a fourth section which follows the third section and in which the start signal of the second voltage level is input and in which the clock signal of the second voltage level is input, a voltage of the first node and the second node is at the second voltage level and a voltage of the third node is at a fourth voltage level, wherein the fourth voltage level is lower than the second voltage level, and an output signal of the second voltage level is output from the output terminal by the fifth transistor when the fifth transistor is turned-on.
12. 12 . The driving circuit of claim 11 , wherein, in a fifth section which follows the fourth section and in which the start signal of the second voltage level is input and in which the clock signal of the first voltage level is input, a voltage of the first node and the second node is at the second voltage level and a voltage of the third node is at the fourth voltage level, and an output signal of the second voltage level is output from the output terminal by the fifth transistor when the fifth transistor is turned-on.
13. 13 . The driving circuit of claim 1 , further comprising a sixth transistor connected between the second node and the third terminal and comprising a gate connected to the third node.
14. 14 . A driving circuit comprising a plurality of stages, wherein each of the plurality of stages comprises: a first transistor connected between a first node and a first terminal through which a start signal is input and which comprises a gate connected to a clock terminal through which a clock signal is input; a second transistor connected between the first node and a second node and which comprises a first gate connected to a second terminal through which a first voltage is supplied and a second gate connected to a third terminal through which a second voltage is supplied; a third transistor connected between the first node and a third node and comprising a gate connected to a fourth terminal through which a third voltage is supplied; a fourth transistor connected between the second terminal and an output terminal and which comprises a first gate connected to the second node and a second gate connected to a fifth terminal through which a fourth voltage is supplied; a fifth transistor connected between the fourth terminal and the output terminal and comprising a gate connected to the third node; a first capacitor connected between the second node and the output terminal; and a second capacitor connected between the third node and the output terminal, wherein the first voltage is a high-level voltage and the third voltage is a low-level voltage.
15. 15 . The driving circuit of claim 14 , further comprising: a sixth transistor connected between the first node and the fourth terminal and comprising a gate connected to a sixth terminal which is configured to supply a reset signal; and a third capacitor connected between the first node and the second terminal.
16. 16 . The driving circuit of claim 14 , further comprising: a seventh transistor connected between the third transistor and the third node and comprising a gate connected to the fourth terminal; and an eighth transistor connected between a fourth node between the third transistor and the seventh transistor and a seventh terminal through which a fifth voltage is supplied and which comprises a gate connected to the third node, wherein the fifth voltage is lower than the third voltage.
17. 17 . The driving circuit of claim 16 , wherein the first transistor, the third transistor, the fifth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and wherein the second transistor and the fourth transistor are N-type transistors.
18. 18 . The driving circuit of claim 14 , wherein the second voltage is equal to the first voltage.
19. 19 . The driving circuit of claim 14 , wherein the third terminal is connected to the first node.
20. 20 . The driving circuit of claim 14 , wherein the fourth voltage is a negative constant voltage having a greater absolute value than the third voltage.

Description

This application claims priority to Korean Patent Application No. 10-2024-0035430, filed on Mar. 13, 2024, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference. BACKGROUND 1. Field The invention relates to a display apparatus, and more particularly, to a driving circuit configured to output a gate signal and a display apparatus including the driving circuit. 2. Description of the Related Art A display apparatus includes a pixel area, a gate driving circuit, a data driving circuit, a controller, and the like, where the pixel area includes a plurality of pixels. The gate driving circuit includes stages connected to gate lines, and the stages respectively supply gate signals to the gate lines connected thereto. SUMMARY One or more embodiments include a driving circuit that is capable of stably outputting a gate signal at low power and a display apparatus that includes the driving circuit. According to one or more embodiments, a driving circuit includes a plurality of stages, wherein each of the plurality of stages includes a first transistor connected between a first node and a first terminal through which a start signal is input and which includes a gate connected to a clock terminal through which a clock signal is input, a second transistor connected between the first node and a second node and including a first gate connected to a second terminal through which a first voltage is supplied and a second gate connected to a third terminal through which a second voltage is supplied, a third transistor connected between the first node and a third node and including a gate connected to the third terminal, a fourth transistor connected between the second terminal and an output terminal and including a first gate connected to the second node and a second gate connected to the third node, a fifth transistor connected between the third terminal and the output terminal and including a gate connected to the third node, a first capacitor connected between the second node and the output terminal, and a second capacitor connected between the third node and the output terminal, wherein the first voltage is a high-level voltage and the second voltage is a low-level voltage. In an embodiment, the driving circuit may further include a sixth transistor connected between the first node and the third terminal and including a gate connected to a fourth terminal configured to supply a reset signal, and a third capacitor connected between the first node and the second terminal. In an embodiment, the first transistor, the third transistor, and the fifth transistor may be P-type transistors, and the second transistor and the fourth transistor may be N-type transistors. In an embodiment, the start signal may include an external signal or an output signal which is output by a previous stage. In an embodiment, the driving circuit may further include a seventh transistor connected between the output terminal and the fifth transistor and including a gate connected to the third node. In an embodiment, the clock signal may alternate between a first voltage level and a second voltage level, where the first voltage level may be a high-level voltage level and the second voltage level may be a low-level voltage level. In an embodiment, a clock signal input to a clock terminal of even-numbered stages among the plurality of stages may be shifted by a half cycle from a clock signal input to a clock terminal of odd-numbered stages. In an embodiment, in a first section in which the start signal of the first voltage level is input and the clock signal of the second voltage level is input, a voltage of the first node and the third node may be at the first voltage level and a voltage of the second node may be at a third voltage level which is higher than the first voltage level, and an output signal of the first voltage level may be output from the output terminal by the turned-on fourth transistor. In an embodiment, in a second section which follows the first section and in which the start signal of the first voltage level is input and in which the clock signal of the first voltage level is input, a voltage of the first node and the third node may be at the first voltage level and a voltage of the second node may be at the third voltage level, and an output signal of the first voltage level may be output from the output terminal by the turned-on fourth transistor. In an embodiment, in a third section which follows the second section and in which the start signal of the second voltage level is input and in which the clock signal of the first voltage level is input, a voltage of the first node and the second node may be at the first voltage level and a voltage of the third node may be at the third voltage level, and an output signal of the first voltage level may be output from the output terminal by the turned-on fourth transistor. In an embodiment, in a fourth section wh