US-12620364-B2 - Gate driving panel circuit and display device

US12620364B2US 12620364 B2US12620364 B2US 12620364B2US-12620364-B2

Abstract

A display device can include a substrate including a display area in which one or more images are displayed and a non-display area different from the display area, and a gate driving panel circuit configured to output a plurality of gate signals to a plurality of gate signal lines disposed in the display area. The gate driving panel circuit can include an output buffer block configured to receive at least one first input signal and output at least one output signal, and a logic block configured to control respective voltages of a Q node and a QB node, which are electrically connected to the output buffer block.

Inventors

Dongmyoung KIM
HongJae Shin
Yongho Kim

Assignees

LG DISPLAY CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20250320
Priority Date: 20230303

Claims (20)

1 . A display device comprising: a substrate including a display area in which one or more images are displayed and a non-display area different from the display area; and a gate driving panel circuit configured to output a plurality of gate signals to a plurality of gate signal lines disposed in the display area, wherein the gate driving panel circuit comprises: an output buffer block configured to receive at least one first input signal and output at least one output signal, and a logic block configured to control respective voltages of a Q node and a QB node, which are electrically connected to the output buffer block, wherein the output buffer block comprises: at least one first transistor, each of which is disposed between a first input node to which the first input signal is input and an output node from which the output signal is output, and at least one second transistor, each of which is disposed between a second input node to which a second input signal different from the first input signal is input and the output node, wherein a gate node of each of the at least one first transistor is electrically connected to the Q node, and wherein the output buffer block comprises at least one first capacitor comprising at least two sub-capacitor regions.
2 . The display device of claim 1 , wherein each of the at least one first capacitor comprises at least two sub-capacitor regions, and each of the at least one first capacitor is disposed between a gate node and a source node of the corresponding first transistor.
3 . The display device of claim 1 , wherein among the first input signal and the second input signal, one is a clock signal and the other is a first gate voltage.
4 . The display device of claim 1 , wherein the at least one first capacitor includes two or more bridge metals disposed between the at least two sub-capacitor regions.
5 . The display device of claim 1 , wherein the gate driving panel circuit further comprises a second capacitor connected to a second gate voltage node.
6 . The display device of claim 5 , wherein the first capacitor has a capacitance greater than the second capacitor, or an area of the first capacitor is greater than an area of the second capacitor.
7 . The display device of claim 1 , wherein the at least one output signal includes a gate signal output to a gate signal line electrically connected to a sub-pixel in the display area among the plurality of gate signal lines, and the at least one first transistor and the at least one second transistor are configured to output the gate signal to the gate signal line disposed in the display area.
8 . The display device of claim 1 , wherein the at least one output signal comprises a carry signal output to other circuit portion in the gate driving panel circuit, and the at least one first transistor and the at least one second transistor are configured to output the carry signal to the other circuit portion.
9 . The display device of claim 1 , wherein each of the at least one first capacitor comprises a first capacitor electrode and a second capacitor electrode, and a capacitance of the first capacitor is determined depending on an area in which the first capacitor electrode and the second capacitor electrode overlap each other.
10 . The display device of claim 9 , wherein: the first capacitor further comprises a third capacitor electrode on the second capacitor electrode; an insulating layer is disposed between the second capacitor electrode and the third capacitor electrode; and the third capacitor electrode is electrically connected to the first capacitor electrode.
11 . The display device of claim 1 , further comprising: a plurality of clock signal lines disposed in a clock signal line area in the non-display area and configured to deliver a plurality of clock signals to the gate driving panel circuit; a plurality of gate high voltage lines disposed in a first power line area in the non-display area and configured to deliver a plurality of gate high voltages to the gate driving panel circuit; and a plurality of gate low voltage lines disposed in a second power line area in the non-display area and configured to deliver a plurality of gate low voltages to the gate driving panel circuit, wherein the gate driving panel circuit is disposed in a gate driving panel circuit area in the non-display area, and the first power line area and the second power line area are separated by at least a portion of the gate driving panel circuit area.
12 . The display device of claim 11 , wherein the plurality of clock signal lines comprise a plurality of gate clock signal lines and a plurality of carry clock signal lines, and a line width of each of the plurality of gate clock signal lines is greater than a line width of each of the plurality of carry clock signal lines, and wherein the plurality of gate clock signal lines comprise a plurality of scan clock signal lines or a plurality of sensing clock signal lines.
13 . The display device of claim 11 , wherein the clock signal line area is located further away from the gate driving panel circuit area than the first power line area.
14 . A gate driving panel circuit comprising: an output buffer block configured to receive at least one first input signal and output at least one output signal; and a logic block configured to control respective voltages of a Q node and a QB node electrically connected to the output buffer block, wherein the output buffer block comprises: at least one first transistor, each of which is disposed between a first input node to which the first input signal is input and an output node to which the output signal is output, and at least one second transistor, each of which is disposed between a second input node to which a second input signal different from the first input signal is applied and the output node, wherein a gate node of each of the at least one first transistor is electrically connected to the Q node, and wherein the output buffer block further comprises at least one capacitor comprising at least two sub-capacitor regions.
15 . The gate driving panel circuit of claim 14 , wherein the at least two sub-capacitor regions share the Q node and the output node.
16 . The gate driving panel circuit of claim 14 , wherein each of the at least one capacitor further comprises: a first capacitor electrode disposed in each of the at least two sub-capacitor regions; a second capacitor electrode disposed in each of the at least two sub-capacitor regions and spaced apart from the first capacitor electrode; and a first bridge interconnecting the respective first capacitor electrodes disposed in the at least two sub-capacitor regions.
17 . The gate driving panel circuit of claim 16 , wherein each the at least one capacitor further comprises: a second bridge interconnecting the respective second capacitor electrodes disposed in the at least two sub-capacitor regions; a third capacitor electrode disposed in each of the at least two sub-capacitor regions and spaced apart from the second capacitor electrode; and a third bridge interconnecting the respective third capacitor electrodes disposed in the at least two sub-capacitor regions.
18 . The gate driving panel circuit of claim 17 , wherein the first capacitor electrode comprises a light shield metal, the second capacitor electrode comprises a gate metal, and the third capacitor electrode comprises a source-drain metal or an anode metal.
19 . The gate driving panel circuit of claim 17 , wherein at least one of the first bridge, the second bridge, and the third bridge is electrically disconnected.
20 . The gate driving panel circuit of claim 16 , wherein the Q node formed from a same light shield metal as the first capacitor electrode is directly connected to at least one of the first capacitor electrodes of the at least two sub-capacitor regions.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a Continuation of U.S. patent application Ser. No. 18/593,260, filed on Mar. 1, 2024, which claims priority to Korean Patent Application No. 10-2023-0028372, filed on Mar. 3, 2023 in the Korean Intellectual Property Office, the entire contents of all these applications being hereby expressly incorporated by reference into the present application. BACKGROUND Technical Field The present disclosure relates to electronic devices with a display, and more specifically, to a gate driving panel circuit and a display device. Discussion of the Related Art A display device can include a display panel in which a plurality of data lines and a plurality of gate lines are disposed, a data driving circuit for outputting data signals to the plurality of data lines, a gate driving circuit for outputting gate signals to the plurality of gate lines, and the like. In order for images to be displayed properly on the display device, gate signals toned to be supplied properly through the plurality of gate lines. For example, in order to present images properly, it is needed for gate driving to be performed properly. However, in a situation where gate driving is not performed properly, image quality can be affected and degraded. SUMMARY OF THE DISCLOSURE One or more embodiments of the present disclosure can provide a gate driving panel circuit having a structure suitable for a gate-in-panel (GIP) type, and a display device including the gate driving panel circuit. One or more embodiments of the present disclosure can provide a gate driving panel circuit suitable for driving gate lines connected to subpixels having a structure capable of allowing sensing to be performed, and a display device including the gate driving panel circuit. One or more embodiments of the present disclosure can provide a gate driving panel circuit having a capacitor structure capable of curing or preventing or minimizing defects such as short circuit which can be caused by undesirable substances or particles, and a display device including the gate driving panel circuit. Short circuit defects caused by undesirable substances or particles can be addressed or prevented by designing capacitors included in an output buffer block and a sensing control block to have a split structure in which each of the capacitors is split into sub-capacitor regions. According to aspects of the present disclosure, a display device can include a substrate including a display area in which one or more images are displayed and a non-display area different from the display area, and a gate driving panel circuit configured to output a plurality of scan signals to a plurality of scan signal lines disposed in the display area. The gate driving panel circuit can include an output buffer block including a scan output buffer configured to receive a clock signal and output a scan signal, and a logic block configured to control respective voltages of a Q node and a QB node, which are electrically connected to the output buffer block. The scan output buffer can include a scan pull-up transistor disposed between a clock node to which the clock signal is input and a scan output node from which the scan signal is output, and a scan pull-down transistor disposed between a gate low voltage node to which a gate low voltage is applied and the output node. The gate node of the scan pull-up transistor can be electrically connected to the Q node. The scan output buffer can further include a first capacitor disposed between the gate node and the source node of the scan pull-up transistor. The first capacitor can be split into at least two sub-capacitor regions. According to aspects of the present disclosure, a gate driving panel circuit can include an output buffer block configured to receive a clock signal and output a scan signal; and a logic block configured to control respective voltages of a Q node and a QB node electrically connected to the output buffer block, wherein the output buffer block comprises a pull-up transistor disposed between a clock node to which the clock signal is input and an output node to which the scan signal is output, and a pull-down transistor disposed between a gate low voltage node to which a gate low voltage is applied and the output node, wherein a gate node of the pull-up transistor is electrically connected to the Q node. Further, the output buffer block further comprises a first capacitor disposed between the gate node and a source node of the pull-up transistor, and the first capacitor comprises at least two sub-capacitor regions. In addition to the aspects above described, other aspects, embodiments and examples of the present disclosure and resulted advantages will be described below, and variations thereof will become apparent to those skilled in the art from the following detailed description. According to one or more embodiments of the present disclosure, a gate driving panel circuit can be provided tha