US-12620365-B2 - Gate driver and display device including same

Abstract

A gate driver according to an embodiment includes a plurality of stages connected to a plurality of gate signal lines. Each of the plurality of stages may include a first transistor connected between a first terminal and an output node and transmitting a voltage of the first terminal to the output node in response to a voltage of a first control node, a second transistor connected between a second terminal and the output node and transmitting a voltage of the second terminal to the output node in response to a voltage of the second control node, and a third transistor diode-connected between the second control node and a third terminal to which a hold signal is input. The hold signal may maintain a first voltage during a first period and maintain a second voltage, different from the first voltage, during a second period.

Inventors

• Hyungjin Song
• NACKHYEON KEUM

Assignees

• SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date

20260505

Application Date

20250331

Priority Date

20240625

Claims (20)

1. 1 . A gate driver, comprising: a plurality of stages connected to a plurality of gate signal lines, wherein each of the plurality of stages comprises: a first transistor connected between a first terminal and an output node and transmitting a voltage of the first terminal to the output node in response to a voltage of a first control node; a second transistor connected between a second terminal and the output node and transmitting a voltage of the second terminal to the output node in response to a voltage of a second control node; and a third transistor diode-connected between the second control node and a third terminal to which a hold signal is input, wherein the hold signal maintains a first voltage during a first period and maintains a second voltage, different from the first voltage, during a second period.
2. 2 . The gate driver of claim 1 , wherein a third voltage is applied to the second terminal, and the first voltage is higher than the third voltage, and the second voltage is lower than the third voltage.
3. 3 . The gate driver of claim 2 , wherein a first clock signal is applied to the first terminal, and the first clock signal is a signal having alternating periods of the first voltage and the third voltage.
4. 4 . The gate driver of claim 2 , wherein the third transistor is turned on when the voltage level of the hold signal is the second voltage.
5. 5 . The gate driver of claim 4 , wherein the second transistor is a p-type transistor.
6. 6 . The gate driver of claim 3 , wherein each of the plurality of stages further includes a first control circuit configured to control a voltage level of the first control node.
7. 7 . The gate driver of claim 6 , wherein the first control circuit comprises: a fourth transistor connected between a fourth terminal through which a start signal is input and a first node, and including a control electrode connected to the first terminal; a fifth transistor connected between the first node and the first control node and including a control electrode connected to the second terminal; a sixth transistor including a first electrode connected to a fifth terminal through which a second clock signal, different from the first clock signal, is input, and a control electrode connected to the first control node; and a first capacitor connected between a second electrode of the sixth transistor and the first control node.
8. 8 . The gate driver of claim 7 , wherein toggling of the first clock signal and the second clock signal is enabled during the first period and disabled during the second period.
9. 9 . The gate driver of claim 3 , wherein each of the plurality of stages further comprises a second control circuit configured to control a voltage level of the second control node.
10. 10 . The gate driver of claim 9 , wherein the second control circuit comprises: a fourth transistor connected between the second terminal and a first node and including a control electrode connected to the first terminal; a fifth transistor connected between the first node and the second node and including a control electrode connected to the second terminal; a sixth transistor connected between a fifth terminal through which a second clock signal, different from the first clock signal, is input and a third node, and including a control electrode connected to the second node; a seventh transistor connected between the third node and the second control node and including a control electrode connected to the fifth terminal; an eighth transistor connected between the first terminal and the second control node and including a control electrode connected to the first control node; a ninth transistor connected between the first node and the first terminal and including a control electrode connected to the first control node; a first capacitor connected between the second node and the third node; and a second capacitor connected between the first terminal and the second control node.
11. 11 . The gate driver of claim 10 , wherein the second control circuit further comprises a tenth transistor connected between the sixth transistor and the third node and including a control electrode connected to the second node.
12. 12 . The gate driver of claim 1 , wherein during the first period a data voltage is written to each pixel, and during the second period no data voltage is written to each pixel.
13. 13 . A display device, comprising: a display panel including a plurality of pixels connected to a plurality of gate signal lines and a plurality of data signal lines; a gate driver including a plurality of stages connected to the plurality of gate signal lines and configured to provide a plurality of gate signals; and a data driver connected to the plurality of data signal lines and configured to provide a plurality of data signals, wherein each of the plurality of stages comprises: a first transistor connected between a first terminal and an output node and transmitting a voltage of the first terminal to the output node in response to a voltage of the first control node; a second transistor connected between a second terminal and the output node and transmitting a voltage of the second terminal to the output node in response to a voltage of the second control node; and a third transistor diode-connected between the second control node and a third terminal to which a hold signal is input, wherein the hold signal maintains a first voltage during a first period and maintains a second voltage, different from the first voltage, during a second period.
14. 14 . The display device of claim 13 , further comprising: a hold signal generator configured to provide the hold signal, wherein the hold signal generator comprises: a fourth terminal to which a hold control signal is input; a fifth terminal through which the hold signal is output; a fourth transistor connected between the fourth terminal and the fifth terminal and including a control electrode connected to a sixth terminal to which a third voltage is input; and a charge pump circuit configured to control a voltage level provided to the fifth terminal in response to the hold control signal and a clock signal.
15. 15 . The display device of claim 14 , wherein the charge pump circuit comprises: a fifth transistor diode-connected between the fourth terminal and a first node; a sixth transistor diode-connected between the first node and the fifth terminal; a seventh transistor including a first electrode to which a first clock signal is input, a second electrode connected to a second node, and a control electrode connected to the fourth terminal; and a capacitor connected between the first node and the second node.
16. 16 . The display device of claim 15 , wherein the charge pump circuit is configured to provide the second voltage lower than the third voltage to the output terminal when the voltage level of the hold control signal is the third voltage.
17. 17 . The display device of claim 13 , wherein a first clock signal is input to the first terminal, a third voltage is input to the second terminal, the first clock signal is a signal having alternating periods of the first voltage and the third voltage, and the first voltage is higher than the third voltage, and the second voltage is lower than the third voltage.
18. 18 . The display device of claim 13 , wherein the third transistor is turned on when the voltage level of the hold signal is the second voltage, and the second transistor is turned on when the second voltage is transmitted to the second control node by the third transistor.
19. 19 . The display device of claim 18 , wherein during the first period a data voltage is written to each pixel, and during the second period no data voltage is written to each pixel.
20. 20 . An electronic device, comprising: a memory; a processor executing an application stored in the memory; and a display device comprising a display module displaying image based on an input image data from the application, wherein the display device comprises: a display panel including a plurality of pixels and displaying image based on an input image data from the application; and a gate driver including a plurality of stages and connected to the plurality of pixels to provide gate signals, wherein each of the plurality of stages comprises: a first transistor connected between a first terminal and an output node and transmitting a voltage of the first terminal to the output node in response to a voltage of the first control node; a second transistor connected between a second terminal and the output node and transmitting a voltage of the second terminal to the output node in response to a voltage of the second control node; and a third transistor diode-connected between the second control node and a third terminal to which a hold signal is input, wherein the hold signal maintains a first voltage during a first period and maintains a second voltage, different from the first voltage, during a second period.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0083178 filed on Jun. 25, 2024, and Korean Patent Application No. 10-2024-0104097 filed on Aug. 5, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. BACKGROUND (a) Field This disclosure relates to a gate driver and a display device including the same. (b) Description of the Related Art A display device displays an image based on image data received from a host processor (e.g., a graphics processing unit GPU or a graphics card). On the other hand, if the rendering frequency of the host processor does not match the driving frequency of the display device, this frequency mismatch may cause a tearing phenomenon in which a boundary line appears in the image displayed on the display device. To prevent this tearing phenomenon, a variable-frequency mode has been developed to synchronize the rendering frequency of the host processor with the driving frequency of the display device. In a display device that supports the variable-frequency mode, the driving sequence of the display panel includes an address scan period during which data voltage is written to the pixel, and a self-scan period during which no data voltage is written to the pixel and only light is emitted. SUMMARY Embodiments of the present disclosure provide a gate driver that may reduce power consumption when a display panel operates in a self-scan mode and a display device including the same. According to an embodiment, a gate driver includes a plurality of stages connected to a plurality of gate signal lines. Each of the plurality of stages includes a first transistor connected between a first terminal and an output node and transmitting a voltage of the first terminal to the output node in response to a voltage of a first control node, a second transistor connected between a second terminal and the output node and transmitting a voltage of the second terminal to the output node in response to a voltage of the second control node, and a third transistor diode-connected between the second control node and a third terminal to which a hold signal is input. The hold signal maintains a first voltage during a first period and maintains a second voltage, different from the first voltage, during a second period. A third voltage may be applied to the second terminal. The first voltage may be higher than the third voltage, and the second voltage may be lower than the third voltage. A first clock signal may be applied to the first terminal. The first clock signal may be a signal having alternating periods of the first voltage and the third voltage alternate. The third transistor may be turned on when the voltage level of the hold signal is the second voltage. The second transistor may be a p-type transistor. Each of the plurality of stages may further include a first control circuit configured to control a voltage level of the first control node. The first control circuit may include a fourth transistor connected between a fourth terminal to which a start signal is input and a first node, and including a control electrode connected to the first terminal, a fifth transistor connected between the first node and the first control node, and including a control electrode connected to the second terminal, a sixth transistor including a first electrode connected to the fifth terminal through which a second clock signal, different from the first clock signal, is input, and a control electrode connected to the first control node, and a first capacitor connected between a second electrode of the sixth transistor and the first control node. Toggling of the first clock signal and the second clock signal may be enabled during the first period and may be disabled during the second period. Each of the plurality of stages may further include a second control circuit configured to control a voltage level of the second control node. The second control circuit may include a fourth transistor connected between the second terminal and the first node and including a control electrode connected to the first terminal, a fifth transistor connected between the first node and the second node and including a control electrode connected to the second terminal, a sixth transistor connected between a fifth terminal through which a second clock signal, different from the first clock signal, is input and a third node, and including a control electrode connected to the second node, a seventh transistor connected between the third node and the second control node and including a control electrode connected to the fifth terminal, an eighth transistor connected between the first terminal and the second control node and including a control electrode connected to the first control node, and a ninth transistor connected between the first node and the first terminal and including a control electrode connec