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US-12620369-B2 - Display substrate and display panel

US12620369B2US 12620369 B2US12620369 B2US 12620369B2US-12620369-B2

Abstract

A display substrate and a display panel are provided, the display substrate includes a first gate driver circuit and a second gate driver circuit that are respectively arranged on a first side and a second side of a display region opposite to each other; the first gate driver circuit includes a plurality of first shift register units arranged in a first direction, each first shift register unit includes a first thin film transistor including a first active layer, the first active layer includes a metal oxide semiconductor material; the second gate driver circuit includes a plurality of second shift register units arranged in the first direction, each second shift register unit includes a second thin film transistor having the same function as the first thin film transistor, and the second thin film transistor includes a second active layer, the second active layer includes a metal oxide semiconductor material.

Inventors

  • Lizhong Wang
  • Guangcai YUAN
  • Ce Ning
  • Hehe HU
  • Nianqi YAO
  • Xin Xie
  • Yifang Huang
  • Liping LEI
  • Chen Xu

Assignees

  • BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date
20260505
Application Date
20240730

Claims (19)

  1. 1 . A display substrate, comprising: a base substrate, and a first gate driver circuit and a second gate driver circuit that are on the base substrate, wherein the display substrate comprises a display region, and the first gate driver circuit and the second gate driver circuit are respectively on a first side of the display region and a second side of the display region that are opposite to each other; the first gate driver circuit comprises a plurality of first shift register units arranged in a first direction, each of the plurality of first shift register units comprises a first thin film transistor having a first function in the first gate driver circuit, the first thin film transistor comprises a first active layer, and the first active layer comprises a metal oxide semiconductor material; the second gate driver circuit comprises a plurality of second shift register units arranged in the first direction, each of the plurality of second shift register units comprises a second thin film transistor having a same function as the first thin film transistor, and the second thin film transistor comprises a second active layer, and the second active layer comprises a metal oxide semiconductor material; the display region comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a pixel driving circuit, and the pixel driving circuit comprises a third thin film transistor; the third thin film transistor comprises a third active layer, wherein the third active layer comprises a plurality of metal oxide semiconductor layers that are stacked, and a material of a metal oxide semiconductor layer close to a gate electrode of the third thin film transistor is amorphous IGZO, and in the amorphous IGZO, In:Ga:Zn is 1:1:1 or 4:2:3; an average threshold voltage of a plurality of first thin film transistors of the plurality of first shift register units is V th1 , and an average threshold voltage of a plurality of second thin film transistors of the plurality of second shift register units is V th2 , then V th1 >V th2 .
  2. 2 . The display substrate according to claim 1 , wherein an average turn-on current of the first thin film transistor of at least one first shift register unit of the plurality of first shift register units is I on1 , and an average turn-on current of the second thin film transistor of at least one second shift register unit of the plurality of second shift register units is I on2 , and I on1 >I on2 .
  3. 3 . The display substrate according to claim 2 , wherein the first thin film transistor and the second thin film transistor are output transistors playing a function of outputting signals, or input transistors playing a function of inputting signals, or reset transistors.
  4. 4 . The display substrate according to claim 3 , wherein the display region further comprises scanning lines connected with the plurality of sub-pixels, and the first thin film transistor and the second thin film transistor are the output transistors playing the function of outputting signals, and are configured to provide gate scanning signals to the scanning lines connected with the plurality of sub-pixels; the scanning lines extend along a second direction, and the second direction is substantially perpendicular to the first direction; the first side and the second side are opposite to each other in the second direction.
  5. 5 . The display substrate according to claim 4 , wherein I on1 −I on2 <I on2 ×20%.
  6. 6 . The display substrate according to claim 4 , wherein the second side has a first region, a second region and a third region that are sequentially arranged along the first direction, an average turn-on current of a plurality of second thin film transistors in the first region is I on21 , an average turn-on current of a plurality of second thin film transistors in the second region is I on22 , and an average turn-on current of a plurality of the second thin film transistors in the third region is I on23 , I on21 >I on22 , and I on23 >I on22 .
  7. 7 . The display substrate according to claim 4 , wherein in a case where gate voltages Vg of a plurality of first thin film transistors are in a range of 10V-20V, turn-on currents of the plurality of first thin film transistors and a plurality of second thin film transistors are all greater than 1200 μA.
  8. 8 . The display substrate according to claim 4 , wherein in a case where gate voltages Vg of a plurality of first thin film transistors are in a range of 10V-20V, a maximum value of turn-on currents of the plurality of first thin film transistors is I on1MAX , a minimum value of the turn-on currents of the plurality of first thin film transistors is I on1MIN , and I on1MAX −I on1MIN ≤1000 μA; in a case where gate voltages Vg of a plurality of second thin film transistors are in a range of 10V-20V, a maximum value of turn-on currents of the plurality of second thin film transistors is I on2MAX , and a minimum value of the turn-on currents of the plurality of second thin film transistors is I on2MIN , and I on2MAX −I on2MIN ≤1000 μA.
  9. 9 . The display substrate according to claim 4 , wherein turn-on currents of a plurality of first thin film transistors of the plurality of first shift register units and a plurality of second thin film transistors of the plurality of second shift register units have a maximum value of I onMAX and a minimum value of I onMIN , it is defined that 3δ 1 =(I onMAX −I onMIN )/(I onMAX +I onMIN ), then 3δ 1 =50˜700.
  10. 10 . The display substrate according to claim 3 , wherein both the first thin film transistor and the second thin film transistor are reset transistors, and gate electrodes of the reset transistors are respectively connected to a reset control signal terminal.
  11. 11 . The display substrate according to claim 10 , wherein I on1 −I on2 <I on2 ×30%.
  12. 12 . The display substrate according to claim 10 , wherein turn-on currents of a plurality of first thin film transistors of the plurality of first shift register units and a plurality of second thin film transistors of the plurality of second shift register units have a maximum value of I onMAX , and a minimum value of I onMIN , it is defined that 3δ 1 =(I onMAX −I onMIN )/(I onMAX +I onMIN ), then 3δ 1 =50˜700.
  13. 13 . The display substrate according to claim 1 , wherein V th1 −V th2 <|V th2 |×30%.
  14. 14 . The display substrate according to claim 1 , wherein in a case where a source-drain input voltage of each of the plurality of first thin film transistors is Vd, Vd=10V-20V and a turn-on current of each of the plurality of first thin film transistors is Id, Id=10 −8 A, | V th1 |<2 V, |V th2 |<2 V.
  15. 15 . The display substrate according to claim 14 , wherein a maximum value of threshold voltages of the plurality of first thin film transistors is V th1MAX , a minimum value of the threshold voltages of the plurality of first thin film transistors is V th1MIN , and V th1MAX −V th1MIN ≤2V; a maximum value of threshold voltages of the plurality of second thin film transistors is V th2MAX , a minimum value of the threshold voltages of the plurality of second thin film transistors is V th2MIN , and V th2MAX −V th2MIN ≤2V.
  16. 16 . The display substrate according to claim 1 , wherein threshold voltages of the plurality of first thin film transistors of the plurality of first shift register units and the plurality of second thin film transistors of the plurality of second shift register units have a maximum value of V thMAX and a minimum value of V thMIN , it is defined that 3δ 2 =(V thMAX −V thMIN )/(V thMAX +V thMIN ), then 3δ 2 =0.1˜2.5.
  17. 17 . The display substrate according to claim 1 , wherein the third active layer, the first active layer and the second active layer are in a same layer.
  18. 18 . The display substrate according to claim 1 , wherein a material of a metal oxide semiconductor layer away from the gate electrode of the third thin film transistor is crystalline IGZO, and in the crystalline IGZO, In:Ga:Zn is 4:2:3 or 1:3:6.
  19. 19 . A display panel, comprising a display substrate and an opposite substrate that are opposite to each other, and a liquid crystal layer between the display substrate and the opposite substrate, wherein the display substrate is the display substrate according to claim 1 .

Description

This application is a continuation application of American patent application Ser. No. 17/908,359 filed on Aug. 31, 2022, which is a national phase of International Application No. PCT/CN2021/115683 filed on Aug. 31, 2021, the entire disclosure of which is incorporated herein by reference as part of the present application. TECHNICAL FIELD Embodiments of the present disclosure relate to a display substrate and a display panel. BACKGROUND With the gradual development of display technology and manufacturing technology, large-size display devices are gradually applied in various aspects of life to meet people's increasing visual needs. For example, for the display panel having a size of 50-inch or more, or even 100-inch or more, the display uniformity of the display panel is an important indicator to evaluate the display effect of the display panel. In the production process of the display panel, the display uniformity affects key indicators such as product performance and yield. SUMMARY At least one embodiment of the present disclosure provides a display substrate, the display substrate comprises a base substrate, and a first gate driver circuit and a second gate driver circuit that are on the base substrate, the display substrate comprises a display region, and the first gate driver circuit and the second gate driver circuit are respectively on a first side of the display region and a second side of the display region that are opposite to each other; the first gate driver circuit comprises a plurality of first shift register units arranged in a first direction, each of the plurality of first shift register units comprises a first thin film transistor having a first function in the first gate driver circuit, the first thin film transistor comprises a first active layer, and the first active layer comprises a metal oxide semiconductor material; the second gate driver circuit comprises a plurality of second shift register units arranged in the first direction, each of the plurality of second shift register units comprises a second thin film transistor having a same function as the first thin film transistor, and the second thin film transistor comprises a second active layer, and the second active layer comprises a metal oxide semiconductor material; an average turn-on current of the first thin film transistor of at least one first shift register unit of the plurality of first shift register units is Ion1, and an average turn-on current of the second thin film transistor of at least one second shift register unit of the plurality of second shift register units is Ion2, and Ion1>Ion2. For example, in the display substrate provided by at least one embodiment of the present disclosure, the first thin film transistor and the second thin film transistor are output transistors playing a function of outputting signals, or input transistors playing a function of inputting signals, or reset transistors. For example, in the display substrate provided by at least one embodiment of the present disclosure, the display region comprises a plurality of sub-pixels and scanning lines connected with the plurality of sub-pixels, and the first thin film transistor and the second thin film transistor are the output transistors playing the function of outputting signals, and are configured to provide gate scanning signals to the scanning lines connected with the plurality of sub-pixels. For example, in the display substrate provided by at least one embodiment of the present disclosure, the scanning lines extend along a second direction, and the second direction is substantially perpendicular to the first direction; the first side and the second side are opposite to each other in the second direction. For example, in the display substrate provided by at least one embodiment of the present disclosure, Ion1−Ion2<Ion2×20%. For example, in the display substrate provided by at least one embodiment of the present disclosure, Ion1−Ion2<Ion2×10%. For example, in the display substrate provided by at least one embodiment of the present disclosure, the second side has a first region, a second region and a third region that are sequentially arranged along the first direction, an average turn-on current of a plurality of second thin film transistors in the first region is Ion21, an average turn-on current of a plurality of second thin film transistors in the second region is Ion22, and an average turn-on current of a plurality of the second thin film transistors in the third region is Ion23, Ion21>Ion22, and Ion23>Ion22. For example, in the display substrate provided by at least one embodiment of the present disclosure, in a case where gate voltages Vg of a plurality of first thin film transistors are in a range of 10V-20V, turn-on currents of the plurality of first thin film transistors and a plurality of second thin film transistors are all greater than 1200 μA. For example, in the display substrate provided by at least one embodiment of the pre