US-12620421-B2 - Memory with reduced leakage through analog head switch control

Abstract

A memory is provided that includes an analog gate voltage driver that drives the gate of a head switch transistor for a bitcell array with an analog gate voltage while the bitcell array operates in a light-sleep mode. The analog gate voltage switches the head switch transistor partially on so that the head switch transistor passes a reduced power supply voltage despite being powered by a memory power supply voltage that is greater than the reduced power supply voltage. The reduced power supply voltage has a sufficient magnitude so that the bitcell array retains its stored binary contents during the light-sleep mode.

Inventors

• Seohee KIM
• Chulmin Jung
• Xiao Chen
• Yi-Ju Chen
• Hanil Lee
• Subbarao Palacharla

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260505

Application Date

20240502

Claims (20)

1. 1 . A memory, comprising: a power supply node for a memory power supply voltage; at least one head switch transistor coupled to the power supply node; a bitcell array coupled between the at least one head switch transistor and ground; a voltage regulator configured to regulate a gate voltage of the at least one head switch transistor during a light-sleep mode for the bitcell array, wherein the voltage regulator includes a replica load circuit configured to replicate a leakage current of the bitcell array during the light-sleep mode, and a replica head switch transistor having a size that is proportional to a size of the at least one head switch transistor, wherein a gate of the replica head switch transistor is coupled to a gate of the at least one head switch transistor, and wherein the voltage regulator further includes a differential amplifier configured to compare a feedback voltage from the replica head switch transistor to a reference voltage to regulate the gate voltage of the replica head switch transistor; and a multiplexer coupled between an output terminal of the differential amplifier and a gate of the at least one head switch transistor.
2. 2 . The memory of claim 1 , wherein the voltage regulator comprises a low dropout regulator.
3. 3 . The memory of claim 1 , wherein the size of the replica head switch transistor equals the size of the at least one head switch transistor.
4. 4 . The memory of claim 1 , wherein the voltage regulator further includes a feedback network to couple the feedback voltage from the replica head switch transistor to the differential amplifier.
5. 5 . The memory of claim 4 , wherein the feedback network comprises a voltage divider.
6. 6 . The memory of claim 1 , further comprising: a voltage reference generator configured to generate the reference voltage.
7. 7 . The memory of claim 6 , wherein the voltage reference generator comprises a bandgap reference generator.
8. 8 . The memory of claim 1 , further comprising: an internal power rail; and a memory periphery, wherein the memory periphery and the bitcell array are coupled between the internal power rail and ground, and wherein the least one head switch transistor comprises a plurality of head switch transistors coupled between the power supply node and the internal power rail.
9. 9 . The memory of claim 8 , wherein the memory periphery includes a plurality of write drivers.
10. 10 . The memory of claim 1 , wherein the multiplexer includes a first transmission gate coupled between the output terminal of the differential amplifier and the gate of the at least one head switch transistor, wherein the first transmission gate is configured to open and close responsive to a light-sleep mode control signal.
11. 11 . The memory of claim 10 , wherein the multiplexer further includes a second transmission gate coupled between a buffer for a digital gate voltage and the gate of the least one head switch transistor, wherein the second transmission gate is configured to open and close responsive to a light-sleep mode control signal in a complementary fashion to the first transmission gate.
12. 12 . The memory of claim 11 , wherein the at least one head switch transistor comprises a p-type metal-oxide semiconductor (PMOS) transistor, and wherein the digital gate voltage equals the memory power supply voltage during a deep-sleep mode for the bitcell array and equals ground during an active mode for the bitcell array.
13. 13 . A memory, comprising: a power supply node for a memory power supply voltage; a first bitcell array; a first head switch transistor coupled between the first bitcell array and the power supply node; and a first multiplexer having an output terminal coupled to a gate of the first head switch transistor, wherein the first multiplexer is configured to select between a digital gate voltage to switch the first head switch transistor fully on during an active mode for the first bitcell array and an analog gate voltage to switch the first head switch transistor partially on during a light-sleep mode for the first bitcell array.
14. 14 . The memory of claim 13 , further comprising: a second bitcell array; a second head switch transistor coupled between the second bitcell array and the power supply node; and a second multiplexer having an output terminal coupled to a gate of the second head switch transistor, wherein the second multiplexer is configured to select between the digital gate voltage to switch the second head switch transistor fully on during an active mode for the second bitcell array and the analog gate voltage to switch the second head switch transistor partially on during a light-sleep mode for the second bitcell array.
15. 15 . The memory of claim 13 , further comprising: a voltage regulator configured to generate the analog gate voltage.
16. 16 . The memory of claim 15 , wherein the voltage regulator comprises a low dropout regulator.
17. 17 . A method of powering a memory, comprising: controlling a gate voltage of a replica head switch transistor coupled between a power supply node for a memory power supply voltage and a replica load to regulate a core power supply voltage provided to the replica load to equal a retention value for the memory, wherein the core power supply voltage is less than the memory power supply voltage; driving a gate of a first head switch transistor coupled between a first bitcell array and the power supply node with the gate voltage to power the first bitcell array with the core power supply voltage, wherein the driving the gate of the first head switch transistor switches the first head switch transistor partially on; and fully switching on a second head switch transistor coupled between a second bitcell array and the power supply node to power the second bitcell array with the memory power supply voltage.
18. 18 . The method of claim 17 , wherein controlling the gate voltage of the replica head switch transistor includes comparing a feedback voltage from the replica load to a reference voltage.
19. 19 . The method of claim 18 , further comprising: powering a periphery of the first bitcell array with the core power supply voltage.
20. 20 . A memory, comprising: a power supply node for a memory power supply voltage; a plurality of head switch transistors coupled to the power supply node; a bitcell array coupled between the plurality of head switch transistors and ground; and means for generating an analog gate voltage of the plurality of head switch transistors to maintain the plurality of head switch transistors partially on during a light-sleep mode for the bitcell array.

Description

TECHNICAL FIELD The present application relates generally to memories and, more specifically, to memories having reduced leakage through analog head switch control. BACKGROUND An integrated circuit with an embedded memory such as a static random-access memory (SRAM) will typically have various operating modes in which a memory power supply voltage for the embedded memory is varied according to the operating mode. With respect to these modes, the integrated circuit may be divided into separate power domains. A core domain (CX) power supply voltage (VDDCX) powers a core domain including a processor whereas a memory domain (MX) power supply voltage (VDDMX) powers the bitcells of the SRAM. But an SRAM does not consist merely of the bitcells but also includes a memory periphery that includes components such as address decoders and other logic. A majority of the memory periphery is contained within the MX domain but there is a CX domain portion of the memory periphery for components such as level-shifters. A memory unit such as an SRAM may thus be divided into a periphery CX domain, a periphery MX domain, and a bitcell domain that is powered by the memory power supply voltage. In the present disclosure, the periphery CX domain and/or the periphery MX domain may be optional for some or all memory units whereas each memory unit comprises (at least) the bitcell domain (also referred to as bitcell array in the following To reduce power consumption and increase battery life, the memory may be placed into a deep-sleep mode in which the bitcell domain, the periphery CX domain, and the periphery MX domain are all powered down. This involves the switching off the head switch transistors that are configured to couple between the power rails for the VDDCX and VDDMX power supply voltages and the corresponding power domains. In a default mode (which may also be denoted as an active mode of operation), the head switch transistors are all on so that the corresponding power domains are all fully powered. In addition, the memory domain power supply voltage VDDMX is sufficiently elevated during the active mode for increased memory speed. During a retention mode, the head switch transistors for the periphery MX and CX domains are powered off. The head switch transistors for the bitcell MX domain remain on so that the bitcells may retain their stored binary content during the retention mode but the memory domain power supply voltage is lowered from its active value to a retention value so that the bitcells have reduced leakage during the retention mode. SUMMARY In accordance with an aspect of the disclosure, a memory is provided that includes: a power supply node for a memory power supply voltage; at least one head switch transistor coupled to the power supply node; a bitcell array coupled between the at least one head switch transistor and ground; and a voltage regulator configured to regulate a gate voltage of the at least one head switch transistor during a light-sleep mode for the bitcell array. In accordance with another aspect of the disclosure, a memory is provided that includes: a power supply node for a memory power supply voltage; a first bitcell array; a first head switch transistor coupled between the first bitcell array and the power supply node; and a first multiplexer having an output terminal coupled to a gate of the first head switch transistor, wherein the first multiplexer is configured to select between a digital gate voltage to switch the first head switch transistor fully on during an active mode for the first bitcell array and an analog gate voltage to switch the first head switch transistor partially on during a light-sleep mode for the first bitcell array. In accordance with yet another aspect of the disclosure, a method of powering a memory is provided that includes: controlling a gate voltage of a replica head switch transistor coupled between a power supply node for a memory power supply voltage and a replica load to regulate a core power supply voltage provided to the replica load to equal a retention value for the memory, wherein the core power supply voltage is less than the memory power supply voltage; and driving a gate of a first head switch transistor coupled between a first bitcell array and the power supply node with the gate voltage to power the first bitcell array with the core power supply voltage Finally, in accordance with another aspect of the disclosure, a memory is provided that includes: a power supply node for a memory power supply voltage; a plurality of head switch transistors coupled to the power supply node; a bitcell array coupled between the plurality of head switch transistors and ground; and means for generating an analog gate voltage of the plurality of head switch transistors to maintain the plurality of head switch transistors partially on during a light-sleep mode for the bitcell array. These and other advantageous features may be better appreciated through the following det