US-12620422-B2 - Data storage circuit and control method thereof, and storage apparatus

US12620422B2US 12620422 B2US12620422 B2US 12620422B2US-12620422-B2

Abstract

Embodiments relate to a data storage circuit and a control method thereof, and a storage apparatus. The data storage circuit includes a first storage array and a sense amplifier array, the first storage array is positioned on a side of the sense amplifier array, and the sense amplifier array is electrically connected to a main bit line. The first storage array includes a plurality of first sub storage arrays, each of the plurality of first sub storage arrays includes a plurality of first sub bit lines and a plurality of first selector switches, each of the plurality of first sub bit lines is electrically connected to the main bit line via one of the plurality of first selector switches, and the sense amplifier array is configured to amplify a signal of the main bit line.

Inventors

Weibing SHANG
Hongwen Li
Liang Chen
Fengqin Zhang
Wei Jiang
Li Tang
Chia-Chi Hsu
HAN-SIH OU

Assignees

CHANGXIN MEMORY TECHNOLOGIES, INC.

Dates

Publication Date: 20260505
Application Date: 20230117
Priority Date: 20210707

Claims (18)

1 . A data storage circuit for DRAM, comprising a first storage array and a sense amplifier array, the first storage array being positioned on a side of the sense amplifier array, a main bit line being electrically connected to the sense amplifier array; the first storage array comprising a plurality of first sub storage arrays, each of the plurality of first sub storage arrays comprising a plurality of first sub bit lines and a plurality of first selector switches arranged in one-to-one correspondence, each of the plurality of first sub bit lines being electrically connected to the main bit line via a corresponding one of the plurality of first selector switches, and each of the plurality of first sub bit lines is controlled independently of the other first sub bit lines by the corresponding one of the plurality of first selector switches; and the sense amplifier array being configured to amplify a signal of the main bit line; and, wherein each memory cell in the first storage array is configured to be read or written via being electrically connected to a single first sub bit line, a number of the plurality of first sub bit lines in each of the plurality of first sub storage arrays is more than two, and a number of the plurality of first selector switches in each of the plurality of first sub storage arrays is more than two, and wherein the plurality of first sub bit lines are further electrically connected to a preset equalization voltage via a plurality of first equalizer switches, and the plurality of first sub bit lines and the plurality of first equalizer switches are arranged in one-to-one correspondence.
2 . The data storage circuit according to claim 1 , wherein the plurality of first sub storage arrays are arranged at equal intervals along a direction away from the sense amplifier array.
3 . The data storage circuit according to claim 2 , wherein each of the plurality of first sub storage arrays has equal number of first sub bit lines.
4 . The data storage circuit according to claim 1 , wherein each of the plurality of first sub storage arrays comprises a plurality of word lines, each of the plurality of first sub storage arrays having equal number of word lines.
5 . The data storage circuit according to claim 1 , wherein each of the plurality of first equalizer switches is configured to: enable a start moment of turn-off earlier, by first preset time, than a start moment of turn-on of the plurality of first selector switches corresponding to a selected one of the plurality of first sub storage arrays.
6 . The data storage circuit according to claim 5 , wherein a first sub bit line corresponding to an unselected first sub storage array is precharged to the preset equalization voltage via a corresponding one of the plurality of first equalizer switches, and a first sub bit line corresponding to the selected one of the plurality of first sub storage arrays is disconnected from the preset equalization voltage to act in cooperation with the sense amplifier array.
7 . The data storage circuit according to claim 1 , further comprising a second storage array, the second storage array being positioned on a side of the sense amplifier array away from the first storage array.
8 . The data storage circuit according to claim 7 , wherein the second storage array comprises a plurality of second sub storage arrays, the plurality of second sub storage arrays having equal number as the plurality of first sub storage arrays, and each of the plurality of second sub storage arrays comprising a plurality of second sub bit lines.
9 . The data storage circuit according to claim 8 , wherein the sense amplifier array is further electrically connected to a complementary main bit line, the plurality of second sub bit lines being electrically connected to the complementary main bit line via second selector switches.
10 . The data storage circuit according to claim 9 , wherein each of the plurality of second sub storage arrays is configured to: when a corresponding one of the plurality of first sub storage arrays is selected, control a corresponding one of the second selector switches to act following a given one of the plurality of first selector switches corresponding to the selected first sub storage array; and otherwise, control a given one of the second selector switches corresponding to an unselected one of the plurality of second sub storage arrays to be turned off.
11 . The data storage circuit according to claim 1 , wherein the first storage array is configured to: when a corresponding one of the plurality of first sub storage arrays is selected, control a given one of the plurality of first selector switches corresponding to the selected first sub storage array to be turned on to electrically connect a corresponding one of the plurality of first sub bit lines and the main bit line, wherein the sense amplifier array is further configured to amplify a signal of the corresponding one of the plurality of first sub bit lines connected to the main bit line; and otherwise, control a given one of the plurality of first selector switches corresponding to an unselected one of the plurality of first sub storage arrays to be turned off.
12 . The data storage circuit according to claim 11 , wherein the sense amplifier array is configured to: begin to amplify the signal of the main bit line within second preset time from a start moment of turn-on of the given first selector switch corresponding to the selected first sub storage array, wherein an end moment of an amplification stage is later, by third preset time, than a start moment of turn-off of the given first selector switch corresponding to the selected first sub storage array.
13 . The data storage circuit according to claim 12 , wherein the sense amplifier array is configured to: enable an end moment of a precharge stage earlier, by fourth preset time, than the start moment of turn-on of the given first selector switch corresponding to the selected first sub storage array.
14 . A storage apparatus, comprising: a plurality of data storage circuits according to claim 1 .
15 . The data storage circuit according to claim 1 , wherein each first sub bit line is electrically connected to a preset equalization voltage via the corresponding first equalizer switch.
16 . The data storage circuit according to claim 1 , wherein each first sub bit line is directly connected to each first equalizer switch.
17 . A method for controlling data storage, applied to a data storage circuit for DRAM, the data storage circuit comprising a sense amplifier array and a first storage array positioned on a side of the sense amplifier array, a main bit line being electrically connected to the sense amplifier array, the first storage array comprising a plurality of first sub storage arrays, each of the plurality of first sub storage arrays comprising a plurality of first sub bit lines and a plurality of first selector switches arranged in one-to-one correspondence, each of the plurality of first sub bit lines being electrically connected to the main bit line via a corresponding one of the plurality of first selector switches, and each of the plurality of first sub bit lines is controlled independently of the other first sub bit lines by the corresponding one of the plurality of first selector switches, wherein each memory cell in the first storage array is configured to be read or written via being electrically connected to a single first sub bit line, a number of the plurality of first sub bit lines in each of the plurality of first sub storage arrays is more than two, and a number of the plurality of first selector switches in each of the plurality of first sub storage arrays is more than two, and wherein the plurality of first sub bit lines are further electrically connected to a preset equalization voltage via a plurality of first equalizer switches, and the plurality of first sub bit lines and the plurality of first equalizer switches are arranged in one-to-one correspondence, the method comprising: controlling a given one of the plurality of first selector switches corresponding to a selected one of the plurality of first sub storage arrays to be turned on to electrically connect a corresponding one of the plurality of first sub bit lines and the main bit line, and controlling a given one of the plurality of first selector switches corresponding to an unselected one of the plurality of first sub storage arrays to be turned off; and controlling the sense amplifier array to be in an amplification stage to amplify a signal of the main bit line, wherein a start moment of the amplification stage is later than a start moment of turn-on of the given first selector switch.
18 . The method according to claim 17 , wherein the plurality of first sub bit lines and the plurality of first selector switches are arranged in one-to-one correspondence, and the sense amplifier array is further configured to amplify a signal of the corresponding one of the plurality of first sub bit lines connected to the main bit line.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present disclosure is a continuation of PCT/CN2022/099828, filed on Jun. 20, 2022, which claims priority to Chinese Patent Application No. 202110768497.1 titled “DATA STORAGE CIRCUIT AND CONTROL METHOD THEREOF, AND STORAGE APPARATUS” and filed to the State Patent Intellectual Property Office on Jul. 7, 2021, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to the field of semiconductor storage technology, and more particularly, to a data storage circuit and a control method thereof, and a storage apparatus. BACKGROUND In general, a semiconductor storage apparatus is arranged in a large two-dimensional array including memory cells. Each row of memory cells may be selected by means of word lines, and each column of memory cells may be selected by means of bit lines. Memory cells positioned at intersections between the word lines and the bit lines are configured to store corresponding data. Sense amplifiers can accurately determine data stored in the memory cells, and are widely used in various storage apparatuses to read the data stored in the memory cells. However, with continuous improvement of storage capacity of a semiconductor storage apparatus in the market, number of memory cells distributed in the semiconductor storage apparatus and number of correspondingly demanded sense amplifiers are constantly increased, resulting in increasing dimension, energy consumption and production costs of the semiconductor storage apparatus. Therefore, how to reduce the dimension, the energy consumption and the production costs of the semiconductor storage apparatus without reducing the storage capacity of the semiconductor storage apparatus becomes one of technical problems to be solved urgently. SUMMARY According to various embodiments of the present disclosure, there are provided a data storage circuit and a control method thereof, and a storage apparatus. According to some embodiments, in one aspect the present disclosure provides a data storage circuit, which includes a first storage array and a sense amplifier array, where the first storage array is positioned on a side of the sense amplifier array, and the sense amplifier array is electrically connected to a main bit line. The first storage array includes a plurality of first sub storage arrays, each of the plurality of first sub storage arrays includes a plurality of first sub bit lines and a plurality of first selector switches, each of the plurality of first sub bit lines is electrically connected to the main bit line via one of the plurality of first selector switches, and the sense amplifier array is configured to amplify a signal of the main bit line. According to some embodiments, the plurality of first sub storage arrays are arranged at equal intervals along a direction away from the sense amplifier array. According to some embodiments, each of the plurality of first sub storage arrays has equal number of first sub bit lines. According to some embodiments, each of the plurality of first sub storage arrays includes a plurality of word lines, and each of the plurality of first sub storage arrays has equal number of word lines. According to some embodiments, the plurality of first sub bit lines are further electrically connected to a preset equalization voltage via a first equalizer switch. According to some embodiments, the first equalizer switch is configured to enable a start moment of turn-off earlier, by first preset time, than a start moment of turn-on of the plurality of first selector switches corresponding to a selected one of the plurality of first sub storage arrays. According to some embodiments, the data storage circuit further includes a second storage array, which is positioned on a side of the sense amplifier array away from the first storage array. According to some embodiments, the second storage array includes a plurality of second sub storage arrays, the plurality of second sub storage arrays have equal number as the plurality of first sub storage arrays, and each of the plurality of second sub storage arrays includes a plurality of second sub bit lines. According to some embodiments, the sense amplifier array is further electrically connected to a complementary main bit line, and the plurality of second sub bit lines are electrically connected to the complementary main bit line via second selector switches. According to some embodiments, each of the plurality of second sub storage arrays is configured to: when a corresponding one of the plurality of first sub storage arrays is selected, control a corresponding one of the second selector switches to act following a given one of the plurality of first selector switches corresponding to the selected first sub storage array; and otherwise, control a given one of the second selector switches corresponding to an unselected one of the plurality of second sub storage arrays to be turned off