US-12620423-B2 - Circuits and methods for sub-bank sharing of external interfaces

US12620423B2US 12620423 B2US12620423 B2US 12620423B2US-12620423-B2

Abstract

An integrated circuit includes a first input/output lane comprising first external terminals and first driver circuits. The first driver circuits exchange signals with a first external device through the first external terminals as part of a first external interface. The first input/output lane is part of a sub-bank in an input/output bank that implements at least a part of the first external interface. The integrated circuit includes a second input/output lane comprising second external terminals and second driver circuits. The second driver circuits exchange signals with a second external device through the second external terminals as part of a second external interface. The second input/output lane is part of the sub-bank in the input/output bank that implements at least a part of the second external interface.

Inventors

Archanna Srinivasan
Arvind Tirumalai
Arch Zaliznyak
Gopal Iyer
Hon Khet Chuah
Arun Patel
Kok Kee Looi

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260505
Application Date: 20211222

Claims (20)

1 . An integrated circuit comprising: a first input/output lane comprising first external terminals and first driver circuits, wherein the first driver circuits transmit first output signals to a first external device through the first external terminals as part of a first external interface in a first input/output bank, and wherein the first input/output lane is part of a first sub-bank of the first input/output bank that implements at least a part of the first external interface; and a second input/output lane comprising second external terminals and second driver circuits, wherein the second driver circuits transmit second output signals to a second external device through the second external terminals as part of a second external interface in the first input/output bank, wherein the second input/output lane is part of the first sub-bank that implements at least a part of the second external interface, and wherein the first sub-bank of the first input/output bank is shared between the first external interface that transmits the first output signals to the first external device and the second external interface that transmits the second output signals to the second external device.
2 . The integrated circuit of claim 1 further comprising: a third input/output lane comprising third external terminals and third driver circuits, wherein the third driver circuits transmit third output signals to the second external device through the third external terminals as part of the second external interface, and wherein the third input/output lane is part of the first sub-bank in the first input/output bank.
3 . The integrated circuit of claim 2 further comprising: a fourth input/output lane comprising fourth external terminals and fourth driver circuits, wherein the fourth driver circuits transmit fourth output signals to the first external device through the fourth external terminals as part of the first external interface, and wherein the fourth input/output lane is part of the first sub-bank in the first input/output bank.
4 . The integrated circuit of claim 1 further comprising: a third input/output lane comprising third external terminals and third driver circuits, wherein the third driver circuits transmit third output signals to the second external device through the third external terminals as part of the second external interface, and wherein the third input/output lane is part of a second sub-bank in a second input/output bank.
5 . The integrated circuit of claim 1 , wherein the first and the second external interfaces are memory interfaces, and wherein the first and the second external devices are memory devices.
6 . The integrated circuit of claim 1 further comprising: a unified fabric interface circuit that phase aligns a clock signal received from the first input/output lane with a data signal received from the first input/output lane.
7 . The integrated circuit of claim 1 further comprising: logic circuits in a core logic region of the integrated circuit; and a selector circuit that is configurable to provide third signals from the first and the second input/output lanes to the logic circuits.
8 . The integrated circuit of claim 7 , wherein the selector circuit is configurable to provide fourth signals from the logic circuits to the first and the second input/output lanes.
9 . The integrated circuit of claim 4 further comprising: a clock network that provides a clock signal from the second input/output lane to each of the second and the third input/output lanes.
10 . A method for sharing a first sub-bank in a first input/output bank with first and second external interfaces, the method comprising: implementing a first input/output lane in the first sub-bank as at least a part of the first external interface to transmit first signals to a first external device through first external terminals using first driver circuits in the first input/output lane; and implementing a second input/output lane in the first sub-bank as at least a part of the second external interface to transmit second signals to a second external device through second external terminals using second driver circuits in the second input/output lane, wherein the first input/output bank is in an integrated circuit, and wherein the first sub-bank in the first input/output bank is shared between the first external interface that transmits the first signals to the first external device and the second external interface that transmits the second signals to the second external device.
11 . The method of claim 10 further comprising: implementing a third input/output lane in the first sub-bank as at least a part of the second external interface to transmit third signals to the second external device through third external terminals using third driver circuits in the third input/output lane.
12 . The method of claim 11 further comprising: implementing a fourth input/output lane in the first sub-bank as at least a part of the first external interface to transmit fourth signals to the first external device through fourth external terminals using fourth driver circuits in the fourth input/output lane.
13 . The method of claim 10 further comprising: implementing a third input/output lane as at least a part of the second external interface to transmit third signals to the second external device through third external terminals using third driver circuits in the third input/output lane, wherein the third input/output lane is part of a second sub-bank in a second input/output bank, and wherein the second input/output bank is in the integrated circuit.
14 . The method of claim 10 further comprising: phase aligning a clock signal received from the first input/output lane with a data signal received from the first input/output lane at a unified fabric interface circuit.
15 . The method of claim 10 further comprising: configuring a selector circuit to provide third signals from the first and the second input/output lanes to logic circuits in a core logic region of the integrated circuit.
16 . The method of claim 15 further comprising: configuring the selector circuit to provide fourth signals from the logic circuits to the first and the second input/output lanes.
17 . The method of claim 13 further comprising: configuring a clock network to provide a clock signal from the second input/output lane to each of the second and the third input/output lanes.
18 . The method of claim 10 , wherein the first and the second external interfaces are memory interfaces, and wherein the first and the second external devices are memory devices.
19 . An integrated circuit package comprising: first and second integrated circuits; and a third integrated circuit comprising a first input/output lane comprising first external terminals and first driver circuits, wherein the first input/output lane is part of a sub-bank in an input/output bank, wherein the first input/output lane implements at least a part of a first external interface, wherein the first driver circuits transmit first signals to the first integrated circuit through the first external terminals, wherein the third integrated circuit further comprises a second input/output lane comprising second external terminals and second driver circuits, wherein the second input/output lane is part of the sub-bank in the input/output bank, wherein the second input/output lane implements at least a part of a second external interface, wherein the second driver circuits transmit second signals to the second integrated circuit through the second external terminals, and wherein the sub-bank in the input/output bank is shared between the first external interface that transmits the first signals to the first integrated circuit and the second external interface that transmits the second signals to the second integrated circuit.
20 . The integrated circuit package of claim 19 , wherein the third integrated circuit further comprises a third input/output lane comprising third external terminals and third driver circuits, wherein the third input/output lane is part of the sub-bank in the input/output bank, and wherein the third driver circuits transmit third signals to the second integrated circuit through the third external terminals as part of the second external interface.

Description

FIELD OF THE DISCLOSURE The present disclosure relates to electronic circuits, and more particularly, to circuits and methods for sub-bank sharing of external interfaces. BACKGROUND Many types of integrated circuit (IC) devices, such as programmable logic IC devices and microprocessor IC devices, communicate with one or more external memory IC devices. The memory IC devices may be in the same package, or coupled to the same circuit board, as the programmable logic or microprocessor IC device. IC devices that communicate with external memory devices typically contain memory interfaces that contain input/output pads and related circuitry. Different memory interfaces in the same IC device may require different power supply voltages. Therefore, input/output (IO) pads are often arranged in input/output (IO) banks in order to support the different memory interfaces. Each IO bank may have its own power supply voltage that is independent of the other IO banks in the IC device. IO buffers within the same IO bank may share the same power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram that illustrates an example of an input/output (IO) bank that can be shared between multiple different external interfaces. FIG. 2 is a diagram that illustrates examples groups of external terminals shown in FIG. 1 that are part of a sub-bank in an IO bank. FIG. 3 is a diagram that illustrates examples of input/output (IO) banks having sub-banks that can be shared between two or more external interfaces. FIG. 4 is a diagram that illustrates other examples of input/output (IO) banks having sub-banks that can be shared between two or more external interfaces. FIG. 5 is a diagram that illustrates an example of a unified fabric interface (UFI) logic circuit. FIG. 6 is a diagram that illustrates an example of a selector circuit that can interface between IO lanes in one or more IO banks and the unified fabric interface (UFI) logic circuit of FIG. 5. FIG. 7 is a diagram that illustrates examples of clock networks that are used to transmit clock signals to IO lanes in sub-banks. FIG. 8 is an example of a programmable logic IC. DETAILED DESCRIPTION One or more specific examples are described below. In an effort to provide a concise description of these examples, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. An integrated circuit (IC) has can only have a limited number of input/output (IO) banks, because of the limitations of the size and the floorplan of the IC die. In the design of each IC, there is often a tradeoff between the number of IO banks in the IC that are used for external memory interfaces, the number of other types of external interfaces, and the cost and die size of the IC. The limited number of input/output banks in an IC die has to satisfy customer requirements for the number and type of external memory interfaces and test features in the IC. In previously known IC dies, each IO bank could only be part of one external memory interface. The external memory interfaces could not be shared to maximize the usage of the external memory interfaces in the IC. Because only one external memory interface could be used for each IO bank, a user of the IC would not be able to support multiple external memory interfaces within a single IO bank. As a result, an IC die could support a fewer number of external memory interfaces. According to some examples disclosed herein, systems and methods are provided for integrated circuits (ICs) having input/output (JO) banks and sub-banks that support sharing between two or more different external interfaces. An IC may have one or more IO banks. Each of the IO banks may include external IO terminals (e.g., JO pads) and related circuitry coupled to each of the external IO terminals, such as input and output driver circuits. Each of the IO banks in the IC may include two or more sub-banks. Each of the sub-banks may include two or more lanes. Each of the lanes may include a subset of the external IO terminals and the related circuitry in the IO bank. Each of the sub-banks in an IO bank may be part of two or more different external interfaces. As an example, one or more lanes in sub-bank may be used as part of a first external interface to exchange signals with one external device, and one or more other lanes in the same sub-bank may be used as part of a secon