US-12620424-B2 - Storage system latch control

US12620424B2US 12620424 B2US12620424 B2US 12620424B2US-12620424-B2

Abstract

A storage system and circuits therefor. A storage system includes a bitcell array comprising a plurality of storage cells arranged in one or more columns and one or more rows; a latch circuit configured to output a latch signal responsive to a latch control signal and a data signal from a global data line during a read operation of a storage cell of the plurality of storage cells; a latch control circuit configured to provide the latch control signal to the latch circuit, where the latch control circuit comprises a first signal propagation path for a first mode of operation and a second signal propagation path for a second mode of operation, and wherein the first signal propagation path is to delay propagation of a pulse signal through the first signal propagation path by a time (Δt) compared to a propagation of the pulse signal through the second propagation path.

Inventors

Sunil KUMAR KROVI
Dharmesh Kumar Sonkar
Rangavdhoot BHUPENDRAKUMAR RAWAL

Assignees

ARM LIMITED

Dates

Publication Date: 20260505
Application Date: 20240320
Priority Date: 20240130

Claims (15)

1 . A storage system comprising: a bitcell array comprising a plurality of storage cells arranged in one or more columns and one or more rows; a latch circuit configured to output a latch signal responsive to a latch control signal and a data signal from a global data line during a read operation of a storage cell of the plurality of storage cells; a latch control circuit configured to provide the latch control signal to the latch circuit, where the latch control circuit comprises a first signal propagation path for a first mode of operation and a second signal propagation path for a second mode of operation, and wherein the first signal propagation path is to delay propagation of a pulse signal through the first signal propagation path by a time (Δt) compared to a propagation of the pulse signal through the second propagation path, wherein one or more properties or characteristics of the first signal propagation path are set to delay the pulse signal by Δt, and wherein the first signal propagation path is enabled responsive to a keeper control signal.
2 . The system of claim 1 , wherein a property or characteristic of the one or more properties or characteristics comprises a length of a delay line along the first signal propagation path.
3 . The system of claim 1 , wherein a property or characteristic of the one or more properties or characteristics comprises a material of a delay line along the first signal propagation path.
4 . The system of claim 1 , wherein a property or characteristic of the one or more properties or characteristics comprises one or more additional components, circuitry or elements along the first signal propagation path compared to the second signal propagation path.
5 . The system of claim 1 , wherein the pulse signal output from the latch control circuit comprises the latch control signal.
6 . The system of claim 5 , wherein the latch control signal comprises a latch enable signal.
7 . The system of claim 1 , wherein the pulse signal comprises a global timing pulse received at an input of the first signal propagation path or the second signal propagation path dependent on the mode of operation.
8 . The system of claim 1 , wherein the latch circuit is configured to generate the latch signal responsive to the latch control signal and the data signal.
9 . The system of claim 1 , wherein, for the second mode of operation, the latch control circuit is configured to provide the latch control signal to the latch circuit, where the latch control signal is to arrive at the latch circuit at substantially the same time as the data signal.
10 . The system of claim 1 , wherein the system comprises a single ended storage system.
11 . A latch control circuit for a storage system configured to provide: a latch control signal to a latch circuit, where the latch control circuit comprises a first signal propagation path for a first mode of operation and a second signal propagation path for a second mode of operation, and where the first signal propagation path is to delay propagation of a pulse signal through the first signal propagation path by a time Δt compared to a propagation of the pulse signal through the second propagation path, wherein one or more properties or characteristics of the first signal propagation path are configured to delay the pulse signal by Δt, and wherein the first signal propagation path is enabled responsive to a keeper control signal.
12 . The latch control circuit of claim 11 , wherein a property or characteristic of the one or more properties or characteristics comprises a length of a delay line along the first signal propagation path.
13 . The latch control circuit of claim 11 , wherein a property or characteristic of the one or more properties or characteristics comprises a material of a delay line along the first signal propagation path.
14 . The latch control circuit of claim 11 , wherein a property or characteristic of the one or more properties or characteristics comprises one or more additional components, circuitry or elements along the first signal propagation path compared to the second signal propagation path.
15 . A method of operating a storage system, the storage system comprising a latch control circuit to provide a latch control signal to a latch circuit during a read operation, the latch circuit having a first mode of operation and second mode of operation, the method comprising: providing a pulse signal as an input to a first signal propagation path in the first mode of operation or providing the pulse signal as an input to a second signal propagation path in a second mode of operation, wherein the first signal propagation path is to delay propagation of the pulse signal through the first signal propagation path by a time Δt compared to propagation of the pulse signal through the second signal propagation path, wherein one or more properties or characteristics of the first signal propagation path are configured to delay the pulse signal by Δt, and wherein the first signal propagation path is enabled responsive to a keeper control signal.

Description

CLAIM TO PRIORITY This application claims priority to Indian application Ser. No. 202411006050 filed Jan. 30, 2024, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD The present techniques relate to a storage system and circuits therefor. In particular, the present techniques relate to circuits for providing a latch control signal for such storage circuits. BACKGROUND A memory circuit may consist of an array of storage or memory cells, where a read bit line (RBL) is coupled to an internal node of a storage cell to allow the data value stored in that storage cell to be read during a read operation. When the RBL is addressed during a read operation, a voltage on the bit line (BL) will either stay at a first voltage level, or will discharge towards a second voltage level, depending on the value stored within the particular storage cell. During a period that a read word line signal is asserted, a sense amplifier connected to the RBL will monitor the voltage on the RBL, and when the voltage transitions to a threshold voltage level between the first and second voltage levels during the read operation, the sense amplifier will determine that the storage cell stores a first value, whilst if it does not transition to the threshold voltage level the sense amplifier will determine that the storage cell stores a second value. During the read operation, a latch circuit receives a latch control signal and data signal and outputs a latch signal in response thereto. The timing of the arrival of the latch control signal and data signal is important for the performance of the storage circuit. SUMMARY The present techniques relate to addressing or mitigating performance issues in storage circuits having latch circuits. In a first approach there is provided a storage system comprising: a bitcell array comprising a plurality of storage cells arranged in one or more columns and one or more rows; a latch circuit configured to output a latch signal responsive to a latch control signal and a data signal from a global data line during a read operation of a storage cell of the plurality of storage cells; a latch control circuit configured to provide the latch control signal to the latch circuit, where the latch control circuit comprises a first signal propagation path for a first mode of operation and a second signal propagation path for a second mode of operation, and wherein the first signal propagation path is to delay propagation of a pulse signal through the first signal propagation path by a time (Δt) compared to a propagation of the pulse signal through the second propagation path. In a further approach there is provided a latch control circuit for a storage system configured to provide: a latch control signal to a latch circuit, where the latch control circuit comprises a first signal propagation path for a first mode of operation and a second signal propagation path for a second mode of operation, and where the first signal propagation path is to delay propagation of a pulse signal through the first signal propagation path by a time Δt compared to a propagation of the pulse signal through the second propagation path. In a further approach there is provided method of operating a storage system, the storage system comprising a latch control circuit to provide a latch control signal to a latch circuit during a read operation, the latch circuit having a first mode of operation and second mode of operation, the method comprising: providing a pulse signal as an input to a first signal propagation path in the first mode of operation or providing the pulse signal as an input to a second signal propagation path in a second mode of operation, wherein the first signal propagation path is to delay propagation of the pulse signal through the first signal propagation path by a time Δt compared to propagation of the pulse signal through the second signal propagation path. In a further approach there is provided a method of providing a latch control circuit for a storage system, the latch control circuit having a first signal propagation path and a second signal propagation path, where the properties or characteristics of the first signal propagation path are defined to delay propagation of a pulse signal through the first signal propagation path by a time Δt compared to a propagation of the pulse signal through the second signal propagation path. In a further approach there is provided a system comprising: the above circuitry, implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board. In a further approach there is provided a chip-containing product comprising the above system assembled on a further board with at least one other product component. In a further approach there is provided a non-transitory computer-readable medium to store computer-readable code for fabrication