US-12620425-B2 - Memory device and method of operating the same

Abstract

A memory device includes: a memory bank module comprising a memory bank; and an operation module comprising a processing in memory (PIM) block, wherein the memory bank comprises: an array of memory cells arranged in a plurality of rows and a plurality of columns; a row buffer configured to store data of a row corresponding to a row address among the plurality of rows; and a selecting module configured to select first data and second data corresponding to a column address from among the data stored in the row buffer, wherein the first data is transmitted to the PIM block through a first data path connected between the selecting module and the PIM block, and the second data is transmitted to the PIM block through a second data path connected between the selecting module and the PIM block.

Inventors

• Sanghoon Cha
• Yuhwan Ro
• Seungwoo Seo

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20231101

Priority Date

20230127

Claims (20)

1. 1 . A memory device, comprising: a memory bank module comprising a memory bank; and an operation module comprising a processing in memory (PIM) block, wherein the memory bank comprises: an array of memory cells arranged in a plurality of rows and a plurality of columns; a row buffer configured to store data of a row corresponding to a row address among the plurality of rows; and a selecting module configured to select, from among the data stored in the row buffer, first data of a first sub-column address and second data of a second sub-column address corresponding to a column address received by the memory device, wherein the first data is transmitted from a first selector of the selecting module to a selector of the PIM block through a first data path connected between the selecting module and the PIM block, and the second data is transmitted from a second selector of the selecting module to another selector of the PIM block through a second data path connected between the selecting module and the PIM block.
2. 2 . The memory device of claim 1 , wherein the column address comprises the first sub-column address and the second sub-column address, a first column group bit is assigned to the first sub-column address, and a second column group bit is assigned to the second sub-column address.
3. 3 . The memory device of claim 2 , wherein the selecting module comprises: the first selector configured to select the first data based on the first sub-column address; and the second selector configured to select the second data based on the second sub-column address.
4. 4 . The memory device of claim 3 , wherein the first selector and the PIM block are connected through the first data path, and the second selector and the PIM block are connected through the second data path.
5. 5 . The memory device of claim 3 , wherein the PIM block is configured to: receive the first data as a first operand from the first selector; receive the second data as a second operand from the second selector; and perform an operation between the first operand and the second operand.
6. 6 . The memory device of claim 5 , wherein the first operand and the second operand are arranged as a pair in the data of the row corresponding to the row address.
7. 7 . The memory device of claim 5 , wherein the PIM block is configured to receive the first operand and the second operand simultaneously.
8. 8 . The memory device of claim 2 , further comprising a multiplexer configured to: receive either one or both of the first column group bit and the second column group bit as a control signal; and output either one or both of the first data and the second data to an outside of the memory device.
9. 9 . The memory device of claim 1 , wherein the PIM block comprises: a register; and a multiplexer configured to select either one or both of data stored in the register and the first data output from the selecting module as a first operand.
10. 10 . The memory device of claim 9 , wherein the PIM block further comprises: another multiplexer configured to select any one of the data stored in either one or both of the register and the second data output from the selecting module as a second operand; and an operator configured to perform an operation between the first operand and the second operand.
11. 11 . The memory device of claim 1 , wherein the memory bank module comprises a dynamic random-access memory (DRAM) bank.
12. 12 . The memory device of claim 1 , wherein: the first selector comprises a multiplexer configured to receive first data corresponding to the memory bank from the memory bank and transmit a first operand to the PIM block; and the second selector comprises another multiplexer configured to receive second data corresponding to the memory bank from the memory bank and transmit a second operand to the PIM block.
13. 13 . The memory device of claim 1 , wherein, for the selecting of the first data and the second data, the selecting module is configured to divide the column address into the first sub-column address and the second sub-column address, the first data corresponds to the first sub-column address and the second data corresponds to the second sub-column address.
14. 14 . The memory device of claim 13 , wherein a bit position of the first data in the first sub-column address corresponds to a bit position of the second data in the second sub-column address.
15. 15 . An electronic device comprising: the memory device of claim 1 ; and a host processor, wherein, for the selecting of the first data and the second data, the selecting module is configured to select the first data and the second data in response to the memory device of claim 1 receiving an instruction from the host processor.
16. 16 . A method of operating a memory device, the method comprising: receiving a row address and a column address; storing data of a row corresponding to the row address in a row buffer of a memory bank of the memory device; selecting, from among the data stored in the row buffer, first data of a first sub-column address and second data of a second sub-column address corresponding to the column address; transmitting the first data from a first selector of the selecting module to a selector of a processing in memory (PIM) block of the memory device through a first data path connected between the memory bank and the PIM block; and transmitting the second data from a second selector of the selecting module to another selector of the PIM block through a second data path connected between the memory bank and the PIM block.
17. 17 . The method of claim 16 , wherein the column address comprises the first sub-column address and the second sub-column address, a first column group bit is assigned to the first sub-column address, and a second column group bit is assigned to the second sub-column address.
18. 18 . The method of claim 17 , wherein the selecting comprises: selecting the first data based on the first sub-column address; and selecting the second data based on the second sub-column address.
19. 19 . The method of claim 18 , further comprising: receiving, by the PIM block, the first data as a first operand; receiving, by the PIM block, the second data as a second operand; and performing, by the PIM block, an operation between the first operand and the second operand.
20. 20 . The method of claim 19 , wherein the first operand and the second operand are arranged as a pair in the data of the row corresponding to the row address.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit under 35 USC § 119(a) of Korean Patent Application No. 10-2023-0010611, filed on Jan. 27, 2023, and Korean Patent Application No. 10-2023-0068327, filed on May 26, 2023, in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference for all purposes. BACKGROUND 1. Field The following description relates to a memory device and a method of operating the same. 2. Description of Related Art A convolutional neural network (CNN), a type of deep neural network (DNN), may be used in various application fields such as, for example, image and signal processing, object recognition, computer vision, and the like. The CNN may be configured to perform a multiply and accumulate (MAC) operation that repeats multiplication and addition using a considerably large number of matrices. When an application of a CNN is executed using general-purpose processors, a plurality of operations that implement a considerable amount of computation but are not complex (such as, for example, a plurality of MAC operations that calculate an inner product of two vectors and accumulates and sum the values) may be performed through processing in memory (PIM). SUMMARY This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. In one or more general aspects, a memory device includes: a memory bank module comprising a memory bank; and an operation module comprising a processing in memory (PIM) block, wherein the memory bank comprises: an array of memory cells arranged in a plurality of rows and a plurality of columns; a row buffer configured to store data of a row corresponding to a row address among the plurality of rows; and a selecting module configured to select first data and second data corresponding to a column address from among the data stored in the row buffer, wherein the first data is transmitted to the PIM block through a first data path connected between the selecting module and the PIM block, and the second data is transmitted to the PIM block through a second data path connected between the selecting module and the PIM block. The column address may include a first sub-column address and a second sub-column address, a first column group bit may be assigned to the first sub-column address, and a second column group bit may be assigned to the second sub-column address. The selecting module may include: a first selector configured to select the first data based on the first sub-column address; and a second selector configured to select the second data based on the second sub-column address. The first selector and the PIM block may be connected through the first data path, and the second selector and the PIM block may be connected through the second data path. The PIM block may be configured to: receive the first data as a first operand from the first selector; receive the second data as a second operand from the second selector; and perform an operation between the first operand and the second operand. The first operand and the second operand may be arranged as a pair in the data of the row corresponding to the row address. The PIM block may be configured to receive the first operand and the second operand simultaneously. The memory device may include a third multiplexer configured to: receive either one or both of the first column group bit and the second column group bit as a control signal; and output either one or both of the first data and the second data to an outside of the memory device. The PIM block may include: a register; and a fourth multiplexer configured to select either one or both of data stored in the register and the first data output from the selecting module as a first operand. The PIM block further may include: a fifth multiplexer configured to select any one of the data stored in either one or both of the register and the second data output from the selecting module as a second operand; and an operator configured to perform an operation between the first operand and the second operand. The memory bank module may include a dynamic random-access memory (DRAM) bank. The memory device may include: a sixth multiplexer configured to receive first data corresponding to the memory bank from the memory bank and transmit a first operand to the PIM block; and a seventh multiplexer configured to receive second data corresponding to the memory bank from the memory bank and transmit a second operand to the PIM block. For the selecting of the first data and the second data, the selecting module may be configured to divide the column address into a first sub-column address and a second sub-column address, the first data may