US-12620427-B2 - Storage device and driving method of storage device based on address conversion

US12620427B2US 12620427 B2US12620427 B2US 12620427B2US-12620427-B2

Abstract

According to one embodiment, there is provided a storage device comprising a first memory chip that includes a plurality of first memory cells and that includes a first circuit configured to perform address conversion by using a conversion function; and a second circuit that is connected to the first memory chip and that is configured to set a first parameter for the first memory chip, wherein when a first address is transmitted to the first memory chip from the second circuit, the first address is converted into a second address by the conversion function using the first parameter, and then one of the plurality of first memory cells that corresponds to the second address in the first memory chip is accessed.

Inventors

Kosuke Hatsuda

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260505
Application Date: 20240304
Priority Date: 20230323

Claims (16)

1 . A storage device comprising: a first memory chip that includes: a plurality of first memory cells, a first address conversion circuit configured to perform address conversion by using first circuitry that applies bitwise inversion to designated bits of an address received by the first address conversion circuit, and a first address decode circuit separate from the first address conversion circuit and first circuitry, the first address decode circuit being configured to decode a converted address that is produced by the first address conversion circuit performing the address conversion using the first circuitry; and a control circuit that is connected to the first memory chip and that is configured to transmit a first parameter to the first memory chip, the first parameter designating bits to be inverted of the address received by the first address conversion circuit, wherein when a first address is transmitted to the first memory chip from the control circuit, the first address conversion circuit receives the first address as the address received by the first address conversion circuit and converts the first address into a second address different from the first address, by bitwise inverting bits of the first address that are designated by the first parameter, and then the first address decode circuit generates a decoded version of the second address, and one of the plurality of first memory cells that corresponds to the decoded version of the second address is accessed.
2 . The storage device according to claim 1 , wherein the first memory chip further includes a register that is configured to store the first parameter.
3 . The storage device according to claim 1 , wherein by converting the first address to the second address, the first address conversion circuit vertically and horizontally changes positions from the first address.
4 . A storage device comprising: a first memory chip that includes: a plurality of first memory cells, an address conversion circuit configured to perform address conversion of an address received by the address conversion circuit, and a redundancy determination circuit configured to perform redundancy determination on a converted address that is produced by the address conversion circuit, the redundancy determination including searching redundancy information for the converted address produced by the address conversion circuit; and a control circuit that is connected to the first memory chip and that is configured to transmit a first parameter to the first memory chip, wherein when a first address is transmitted to the first memory chip from the control circuit, the address conversion circuit receives the first address as the address received by the address conversion circuit and converts the first address into a second address based on the first parameter, the redundancy determination circuit performs the redundancy determination on the second address as the converted address that is produced by the address conversion circuit, after the first address is converted into the second address, and one of the plurality of first memory cells that corresponds to the second address is accessed after the redundancy determination circuit performs the redundancy determination on the second address.
5 . The storage device according to claim 4 , wherein the redundancy information identifies a plurality of defective memory cells of the first memory chip, and the redundancy determination performed on the second address comprises the redundancy determination circuit determining whether the second address corresponds to one of the plurality of defective memory cells of the first memory chip.
6 . The storage device according to claim 1 , further comprising: a second memory chip connected to the control circuit, the second memory chip including: a plurality of second memory cells, a second address conversion circuit configured to perform address conversion by using second circuitry that applies bitwise inversion to designated bits of an address received by the second address conversion circuit, and a second address decode circuit configured to decode a converted address that is produced by the second address conversion circuit performing the address conversion using the second circuitry, wherein the control circuit is further configured to transmit a second parameter to the second memory chip, the second parameter designating bits to be inverted of the address received by the second address conversion circuit, and when the first address is transmitted to the second memory chip from the control circuit, the second address conversion circuit receives the first address as the address received by the second address conversion circuit and converts the first address into a third address different from the first address, by bitwise inverting bits of the first address that are designated by the second parameter, and then the second address decode circuit generates a decoded version of the third address, and one of the plurality of second memory cells corresponding to the decoded version of the third address is accessed.
7 . The storage device according to claim 6 , wherein the second parameter is an integer larger than the first parameter.
8 . The storage device according to claim 6 , further comprising: a third memory chip connected to the control circuit, the third memory chip including: a plurality of third memory cells, a third address conversion circuit configured to perform address conversion by using third circuitry that applies bitwise inversion to designated bits of an address received by the third address conversion circuit, and a third address decode circuit configured to decode a converted address that is produced by the third address conversion circuit performing the address conversion using the third circuitry, wherein the control circuit is further configured to transmit a third parameter to the third memory chip, the third parameter designating bits to be inverted of the address received by the third address conversion circuit, and when the first address is transmitted to the third memory chip from the control circuit, the third address conversion circuit receives the first address as the address received by the third address conversion circuit and converts the first address into a fourth address different from the first address, by bitwise inverting bits of the first address that are designated by the third parameter, and then the third address decode circuit generates a decoded version of the fourth address, and one of the plurality of third memory cells that corresponds to the decoded version of the fourth address is accessed.
9 . The storage device according to claim 8 , wherein the second address is different from the third address, and the second parameter is an integer larger than the first parameter, and the third parameter is an integer larger than the second parameter.
10 . The storage device according to claim 9 , wherein a difference between the second parameter and the first parameter is equal to a difference between the third parameter and the second parameter.
11 . The storage device according to claim 9 , wherein a difference between the second parameter and the first parameter is different from a difference between the third parameter and the second parameter.
12 . The storage device according to claim 8 , wherein the second address is the same as the third address, and the second parameter is an integer that is larger than the first parameter and that has the same value as the third parameter.
13 . The storage device according to claim 1 , wherein the plurality of first memory cells includes a variable resistance element.
14 . The storage device according to claim 13 , wherein the variable resistance element is a magnetoresistance effect element.
15 . A driving method of a storage device that comprises a first memory chip and a control circuit, the first memory chip including a plurality of first memory cells, an address conversion circuit configured to perform address conversion of an address received by the address conversion circuit, and a redundancy determination circuit configured to perform redundancy determination on a converted address that is produced by the address conversion circuit, the redundancy determination including searching redundancy information for the converted address produced by the address conversion circuit, the control circuit being connected to the first memory chip, the driving method comprising: transmitting, by the control circuit, a first parameter to the first memory chip; when a first address is transmitted to the first memory chip from the control circuit, receiving, by the address conversion circuit, the first address as the address received by the address conversion circuit, and then converting, by the address conversion circuit, the first address into a second address based on the first parameter; performing, by the redundancy determination circuit, the redundancy determination on the second address as the converted address that is produced by the address conversion circuit, after the first address is converted into the second address; and accessing one of the plurality of first memory cells that corresponds to the second address after the redundancy determination circuit performs the redundancy determination on the second address.
16 . The driving method according to claim 15 , wherein the redundancy information identifies a plurality of defective memory cells of the first memory chip, and the redundancy determination performed on the second address comprises the redundancy determination circuit determining whether the second address corresponds to one of the plurality of defective memory cells of the first memory chip.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-046848, filed Mar. 23, 2023, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a storage device and a driving method of the storage device. BACKGROUND A storage device using a variable resistance element as a storage element is known. For example, a magnetoresistive random access memory (MRAM) in which a magnetoresistance effect element is used as a variable resistance element is known. DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an example of a configuration of the memory system including a storage device according to a first embodiment. FIG. 2 is a block diagram showing an example of a configuration of a memory chip provided in the storage device according to the first embodiment. FIG. 3 is a circuit diagram showing an example of a configuration of a memory cell array in the storage device according to the first embodiment. FIG. 4 is a cross-sectional view showing an example of a structure of a magnetoresistance effect element provided in the storage device according to the first embodiment. FIG. 5 is a circuit diagram showing an example of a configuration of an address conversion circuit in a memory chip provided in the storage device according to the first embodiment. FIG. 6 is a diagram illustrating an example of a specific process of a conversion function used in an address conversion circuit provided in the storage device according to the first embodiment. FIG. 7 is a diagram illustrating another example of the specific processing of the conversion function used in the address conversion circuit provided in the storage device according to the first embodiment. FIG. 8 is a diagram showing a relationship between a memory cell designated by an address before address translation and a memory cell designated by an address after address translation in FIG. 7. FIG. 9 is a flowchart showing an example of a setting operation of the storage device according to the first embodiment. FIG. 10 is a flowchart showing an example of an address conversion operation of a chip provided in the storage device according to the first embodiment. FIG. 11 is a diagram showing an error detection result in the storage device of the comparative example and the storage device according to the first embodiment. FIG. 12 is a diagram illustrating an example of a specific process of a conversion function used in an address conversion circuit provided in the storage device according to the first modification example of the first embodiment. FIG. 13 is a diagram showing a relationship between a memory cell designated by an address before address conversion and a memory cell designated by an address after address conversion in FIG. 12. FIG. 14 is a diagram illustrating another example of the specific process of the conversion function used in the address conversion circuit provided in the storage device according to the first modification example of the first embodiment. FIG. 15 is a diagram showing a relationship between a memory cell designated by an address before address conversion and a memory cell designated by an address after address conversion in FIG. 14. FIG. 16 is a circuit diagram showing an example of a configuration of an address conversion circuit in a memory chip provided in the storage device according to the second modification example of the first embodiment. FIG. 17 is a diagram illustrating an example of a specific process of a conversion function used in an address conversion circuit provided in the storage device according to the second modification example of the first embodiment. FIG. 18 is a diagram showing a relationship between a memory cell designated by an address before address conversion and a memory cell designated by an address after address conversion in FIG. 17. FIG. 19 is a diagram illustrating another example of the specific process of the conversion function used in the address conversion circuit provided in the storage device according to the second modification example of the first embodiment. FIG. 20 is a diagram showing a relationship between a memory cell designated by an address before address conversion and a memory cell designated by an address after address conversion in FIG. 19. FIG. 21 is a conceptual diagram showing an example of redundancy information stored in the storage device according to the second embodiment. FIG. 22 is a block diagram showing an example of a configuration of a memory chip provided in the storage device according to the second embodiment. FIG. 23 is a flowchart showing an example of a redundancy determination operation of a memory chip provided in the storage device according to the second embodiment. DETAILED DESCRIPTION Embodiments provide a storage device and a driving method of the storage device capable of reducing a defect r