US-12620428-B2 - Selector only memory write operation

Abstract

Technology for programming selector-only memory cells in a cross-point memory structure. The threshold switching memory element may include, but is not limited to, an Ovonic Threshold Switch (OTS). The memory system removes Vth drift in the threshold switching memory elements prior to programming. The Vth drift is removed by applying a first voltage and a second voltage having opposite polarities to all of the SOM cells to be programmed. Then, two programming voltages having the two polarities are applied to program the cells to two states.

Inventors

• Mark Lin
• Dimitri Houssameddine
• Raj Ramanujan
• Christopher J. Petti

Assignees

• SanDisk Technologies, Inc.

Dates

Publication Date

20260505

Application Date

20240627

Claims (20)

1. 1 . An apparatus comprising: one or more control circuits configured to connected to a cross-point structure having self-selecting memory cells, each self-selecting memory cell having a threshold switching selector, the one or more control circuits configured to: apply a first signal having a first polarity to a group of memory cells selected for programming, the first signal switches on the threshold switching selectors in a first set of the memory cells; apply a second signal having a second polarity to the group of memory cells selected for programming, the second signal switches on the threshold switching selectors in a second set of the memory cells; apply a third signal having the first polarity to a third set of the group of memory cells after applying both the first signal and the second signal to the group of the memory cells, the third signal programs the threshold switching selectors in the third set of the memory cells to a first state; and apply a fourth signal having the second polarity to a fourth set of the group of memory cells after applying both the first signal and the second signal to the group of the memory cells, the fourth signal programs the threshold switching selectors in the fourth set of the memory cells to a second state.
2. 2 . The apparatus of claim 1 , wherein the one or more control circuits are configured to establish a magnitude of the first signal to create a maximum voltage across the memory cells in the group between a first highest drifted threshold voltage of memory cells in the group that were most recently programmed to the first state and a second highest drifted threshold voltage of memory cells in the group that were most recently programmed to the second state.
3. 3 . The apparatus of claim 1 , wherein the one or more control circuits are configured to establish a magnitude of the first signal to create a maximum voltage across the memory cells in the group at a midpoint between a first highest drifted threshold voltage for memory cells in the group programmed to a low threshold voltage state and second highest drifted threshold voltage for memory cells in the group programmed to a high threshold voltage state.
4. 4 . The apparatus of claim 1 , wherein the first set of the memory cells were most recently programmed to the first state, the first signal has a magnitude and polarity that switches on the threshold switching selectors of memory cells most recently programmed to the first state but does not switch on the threshold switching selectors of memory cells most recently programmed to the second state.
5. 5 . The apparatus of claim 1 , wherein the first signal has a magnitude and polarity to remove drift in threshold voltages of the threshold switching selectors of the first set of the memory cells but does not switch on the threshold switching selectors in the second set of the memory cells.
6. 6 . The apparatus of claim 5 , wherein the second signal has a magnitude and polarity to remove drift in threshold voltages of the threshold switching selectors of the second set of the memory cells that were most recently programmed to the second state.
7. 7 . The apparatus of claim 1 , wherein: the first signal has a magnitude to demarcate between the first state and the second state; and the second signal has the magnitude to demarcate between the first state and the second state.
8. 8 . The apparatus of claim 1 , wherein the wherein the one or more control circuits are configured to concurrently apply the third signal to the third set of the group of memory cells and the fourth signal to the fourth set of the group of memory cells.
9. 9 . The apparatus of claim 1 , wherein the one or more control circuits are configured to: apply the third signal to the third set of the memory cells and the fourth signal to the fourth set of the memory cells without determining memory cell states in response to either the first signal or the second signal.
10. 10 . The apparatus of claim 1 , wherein the first signal and the second signal are voltages having substantially the same magnitude.
11. 11 . The apparatus of claim 1 , wherein the first signal and the second signal are currents having substantially the same magnitude.
12. 12 . A method for operating a cross-point memory structure having self-selecting memory cells, the method comprising: applying a first read signal to a group of the memory cells that triggers memory cells that were most recently programmed to a first state but does not trigger memory cells were most recently programmed to a second state, the first read signal having a first polarity and creating a first maximum voltage across each particular cell in the group; applying a second read signal to the group of the memory cells after applying the first read signal to the group, the second read signal having a second polarity opposite the first polarity and creating the first maximum voltage across each particular cell in the group; applying a first write signal to a first set of the group of memory cells to write the first set to the first state after applying both the first read signal and the second read signal to the group of the memory cells, the first write signal having the first polarity; and applying a second write signal to a second set of the group of memory cells to write the second set to the second state after applying both the first read signal and the second read signal to the group of the memory cells, the second write signal having the second polarity.
13. 13 . The method of claim 12 , further comprising: establishing a magnitude of the first read signal to create a maximum voltage across the memory cells in the group between a first highest drifted threshold voltage of memory cells in the group that were most recently programmed to the first state and a second highest drifted threshold voltage of memory cells in the group that were most recently programmed to the second state.
14. 14 . The method of claim 12 , further comprising: establishing a magnitude of the first read signal to create a maximum voltage across the memory cells in the group at a midpoint between a first highest drifted threshold voltage for memory cells programmed to a low threshold voltage state and second highest drifted threshold voltage for memory cells programmed to a high threshold voltage state.
15. 15 . The method of claim 12 , wherein applying the first write signal to the first set of the group and applying the second write signal to the second set of the group are performed without determining memory cell states in response to either the first read signal or the second read signal.
16. 16 . A memory system comprising: a cross-point memory structure having first conductive lines, second conductive lines, and memory cells, each memory cell at a junction of one of the first conductive lines and one of the second conductive lines, each memory cell having a threshold switching selector; one or more control circuits in communication with the cross-point memory structure, the one or more control circuits configured to: cause a first voltage across each memory cell in a group of memory cells selected for programming, the first voltage having a first maximum magnitude and a first polarity that reduces threshold voltage drift in the threshold switching selectors in memory cells in the group that were most recently programmed to a first state; cause a second voltage across each memory cell in the group of memory cells following causing the first voltage to the group of memory cells, the second voltage having substantially the first maximum magnitude and a second polarity opposite the first polarity; cause a third voltage having the first polarity across each memory cell in a first set of memory cells in the group to write the threshold switching selectors in the first set of memory cells to the first state, the third voltage caused after causing both the first voltage and the second voltage; and cause a fourth voltage having the second polarity across each memory cell in the group in a second set of memory cells in the group to write the threshold switching selectors in the second set of memory cells to a second state, the fourth voltage caused after causing both the first voltage and the second voltage.
17. 17 . The memory system of claim 16 , wherein the one or more control circuits are configured to cause the first maximum magnitude for the first voltage between a first highest drifted threshold voltage of the memory cells most recently programmed to the first state and a second highest drifted threshold voltage of memory cells most recently programmed to the second state.
18. 18 . The memory system of claim 16 , wherein the one or more control circuits are configured to cause the first maximum magnitude for the first voltage at a midpoint between a first highest drifted threshold voltage for memory cells programmed to a low threshold voltage state and second highest drifted threshold voltage for memory cells programmed to a high threshold voltage state.
19. 19 . The memory system of claim 16 , wherein the one or more control circuits are configured to: cause the first maximum magnitude for the first voltage to refresh drifted threshold voltages of the memory cells most recently programmed to the first state without triggering the threshold switching selector in the memory cells most recently programmed to the second state.
20. 20 . The memory system of claim 16 , wherein the one or more control circuits are configured to: concurrently cause the third voltage across memory cells in the first set and the fourth voltage across memory cells in the second set.

Description

BACKGROUND Memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). The memory cells may reside in a cross-point memory array. In a memory array with a cross-point type architecture, one set of conductive lines run across the surface of a substrate and another set of conductive lines are formed above the other set of conductive lines running in an orthogonal direction relative to the initial layer. The memory cells are located at the cross-point junctions of the two sets of conductive lines. Cross-point memory arrays are sometimes referred to as cross-bar memory arrays. One type of memory cell contains a programmable resistance memory element, such as magnetoresistive memory element. A magnetoresistive random access memory (MRAM) cell uses magnetization to represent stored data. A bit of data is written to an MRAM cell by changing the direction of magnetization of a magnetic element (“the free layer”) within the MRAM cell, and a bit is read by measuring the resistance of the MRAM cell, such resistance changing with the direction of magnetization. However, the cross-point memory array may have other types of memory cells. For example, the cross-point memory array may have memory cell of other technologies such as ReRam, PCM (Phase Change Memory), or FeRam. In some cross-point memory architectures, each memory cell contains a threshold switching selector in series with a programmable resistance memory element. In such an architecture, the programmable resistance memory element is programmed to store data, whereas the threshold switching selector is used to select the memory cell. The threshold switching selector has a high resistance (in an off or non-conductive state) until it is biased to a voltage higher than its threshold voltage (Vt) or current above its threshold current, (It), and until its voltage bias falls below Vhold (“Voffset”) or current below a holding current Ihold. After the Vt is exceeded and while Vhold is exceeded across the threshold switching selector, the threshold switching selector has a relatively lower resistance (in an on or conductive state). The threshold switching selector remains on until its current is lowered below a holding current Ihold, or the voltage is lowered below a holding voltage, Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. One example of a threshold switching selector is an Ovonic Threshold Switch (OTS). Other examples of threshold switching selectors include, but are not limited to, Volatile Conductive Bridge (VCB), Metal-Insulator-Metal (MIM), or other material that provides a highly non-linear dependence of current on select voltage. In some cross-point architectures, the memory cell contains a threshold switching selector that is used as both a selector and the programmable memory element. Such architectures may be referred to as either a selector only memory (SOM) cell or a self-selecting memory cell. The threshold voltage (Vth) of a SOM cell when reading with a voltage of a given polarity may depend on the polarity of the write voltage used to program the SOM cell. A SOM cell that is written and read with the same polarity voltage may exhibit a lower Vth than if the SOM cell is written and read with opposite polarity voltages. The memory system may assign a default polarity to the read voltage, which allows the SOM cell to be programmed to a first state using a first polarity write voltage and to a second state with a second polarity write voltage opposite the first polarity. However, over time the Vth of the threshold switching selector may drift, which presents technical challenges. FIG. 1A depicts a graph of threshold voltages of SOM cells over time. FIG. 1B is a table that shows a conventional programming scheme used in connection with the SOM cells. In this programming scheme state, W0 is written with the same polarity voltage as the read voltage. However, state W1 is written with the opposite polarity voltage as the read voltage. Read may be performed with a default polarity voltage. The read voltage polarity may be selected by the memory system, but will be the same with each read. Column 60 shows the last voltage that applied to the memory cell, which resulted in the cell firing (e.g., switching on the selector). The up-arrows and down-arrows in the table in FIG. 1B are used to represent the relative polarities of the voltages. Column 62 shows the new data to be written to the cell. Referring now to FIG. 1A, SOM cells programmed to state W0 (with “down-polarity write voltage”) and read immediately (with the “down-polar