US-12620429-B2 - Semiconductor memory, refresh method and electronic device

Abstract

A semiconductor memory, a refresh method and an electronic device are provided. The semiconductor memory includes a main storage area and a mark storage area, multiple storage rows are arranged in the main storage area, and multiple first flag bits are arranged in the mark storage area. Each storage row has a correspondence with one first flag bit, and the first flag bit is used for indicating whether the storage row is an aggressor row of a row hammer event.

Inventors

• HUAN LU

Assignees

• CHANGXIN MEMORY TECHNOLOGIES, INC.

Dates

Publication Date

20260505

Application Date

20220927

Priority Date

20220408

Claims (7)

1. 1 . A semiconductor memory, comprising: a main storage area and a mark storage area, a plurality of storage rows being arranged in the main storage area, and a plurality of first flag bits being arranged in the mark storage area, wherein each storage row has a correspondence with one first flag bit, and the first flag bit is used for indicating whether the storage row is an aggressor row of a row hammer event; wherein the plurality of storage rows are divided into a plurality of storage groups, and a plurality of second flag bits are further arranged in the mark storage area; each storage group has a correspondence with one second flag bit, and the second flag bit is at least used for indicating whether at least one memory cell in the storage group has a specific state, the specific state comprising an occupancy state.
2. 2 . The semiconductor memory of claim 1 , wherein a portion of the storage row extending to the mark storage area is used for forming a first flag bit corresponding to the storage row; wherein the first flag bit occupies a memory cell.
3. 3 . The semiconductor memory of claim 1 , wherein the semiconductor memory is configured to: adjust, in response to monitoring that a number of consecutive accesses to a storage row within a unit time exceeds a preset threshold, a first flag bit of the storage row to a first state; or, adjust, after performing a refresh operation on adjacent storage rows of the storage row, the first flag bit of the storage row to a second state, and reaccumulate the number of consecutive accesses to the storage row within the unit time.
4. 4 . The semiconductor memory of claim 1 , wherein each storage group comprises one storage row, and a portion of the storage row extending to the mark storage area is used for forming a second flag bit corresponding to the storage group; or each storage group comprises a plurality of storage rows, and a portion of one of the storage rows extending to the mark storage area is used for forming a second flag bit corresponding to the storage group.
5. 5 . The semiconductor memory of claim 1 , wherein the semiconductor memory is further configured to: adjust, after receiving a memory allocation instruction for a memory cell, a second flag bit of a storage group comprising the memory cell to a third state; or, adjust, after receiving a memory release instruction for the storage group, the second flag bit of the storage group to a fourth state; or, adjust, after performing a refresh operation on the storage group, the second flag bit of the storage group to the fourth state; wherein the memory allocation instruction is a word line activation instruction or constructed by using a first reserved code in a memory controller, and the memory release instruction is constructed by using a second reserved code in the memory controller.
6. 6 . An electronic device, at least comprising the semiconductor memory of claim 1 .
7. 7 . The electronic device of claim 6 , wherein the semiconductor memory is a Dynamic Random Access Memory (DRAM) chip.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation of International Patent Application No. PCT/CN2022/098668, filed on Jun. 14, 2022, which claims priority to Chinese patent application No. 202210370026.X, filed on Apr. 8, 2022 and entitled “SEMICONDUCTOR MEMORY, REFRESH METHOD AND ELECTRONIC DEVICE”. The contents of International Patent Application No. PCT/CN2022/098668 and Chinese patent application No. 202210370026.X are incorporated herein by reference in their entireties. BACKGROUND Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, which consists of multiple repeated memory cells, and different memory cells need to be selected through word lines and bit lines. That is, there are a large number of word lines in DRAM, which are arranged adjacent to each other. When a certain word line is subjected to a row hammer, memory cells on word lines adjacent to the word line may produce data errors. In order to solve the problem, it is necessary to refresh the word lines after the row hammer is detected. In such case, a refresh object is randomly determined, which results in insignificant mitigation on the row hammer attack and high power consumption. SUMMARY The present disclosure relates to the technical field of semiconductor memory, and provides a semiconductor memory, a refresh method and an electronic device, which may mark an aggressor row of a row hammer event through a first flag bit, so as to improve the handling effect of the row hammer event. The technical solution of the present disclosure is realized as follows. According to a first aspect, the embodiments of the present disclosure provide a semiconductor memory, which includes a main storage area and a mark storage area. Multiple storage rows are arranged in the main storage area, and multiple first flag bits are arranged in the mark storage area. Each storage row has a correspondence with one first flag bit, and the first flag bit is used for indicating whether the storage row is an aggressor row of a row hammer event. According to a second aspect, the embodiments of the present disclosure provide a refresh method, which is applied to a semiconductor memory including multiple storage rows and multiple first flag bits, and one of the first flag bits is used for indicating whether one storage row is an aggressor row of a row hammer event. The method includes the following operations. A target storage row is randomly determined in the multiple storage rows after a hammer refresh instruction is received. A first flag bit of the target storage row is read to obtain a read result. It is determined according to the read result whether to perform a refresh operation on adjacent storage rows of the target storage row. According to a third aspect, the embodiments of the present disclosure provide a refresh method, which is applied to a semiconductor memory including multiple storage rows and multiple first flag bits, and one of the first flag bits is used for indicating whether one storage row is an aggressor row of a row hammer event. The method includes the following operations. First flag bits of the multiple storage rows are read after a hammer refresh instruction is received, to obtain a read result. Candidate storage rows are determined in the multiple storage rows according to the read result. Storage rows to be refreshed are determined according to the candidate storage rows, and a refresh operation is performed on the storage rows to be refreshed. According to a fourth aspect, the embodiments of the present disclosure provide an electronic device, which includes the semiconductor memory as described in the first aspect. The embodiments of the present disclosure provide a semiconductor memory, a refresh method and an electronic device. The semiconductor memory includes a main storage area and a mark storage area, multiple storage rows are arranged in the main storage area, and multiple first flag bits are arranged in the mark storage area. Each storage row has a correspondence with one first flag bit, and the first flag bit is used for indicating whether the storage row is an aggressor row of a row hammer event. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic timing diagram of a refresh operation. FIG. 2 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present disclosure. FIG. 3 is a first schematic diagram of a specific structure of a semiconductor memory according to an embodiment of the present disclosure. FIG. 4 is a schematic structural diagram of another semiconductor memory according to an embodiment of the present disclosure. FIG. 5 is a second schematic diagram of a specific structure of a semiconductor memory according to an embodiment of the present disclosure. FIG. 6 is a third schematic diagram of a specific structure of a semiconductor memory according to an embodiment of the present disclosure. FIG. 7 is a first schematic fl