US-12620430-B2 - Apparatuses and methods for monitored refresh management operations

Abstract

A controller performs an access operation on a word line which is in a portion of a memory array in a memory device. The controller counts accesses on a portion-by-portion basis (e.g., a bank-by-bank basis, a sub-bank-by-sub-bank basis, etc.). The memory counts accesses on a word line-by-word line basis. The memory sets a refresh management (RFM) flag for a portion based on the counts associated with the word lines in that portion. The controller checks the RFM flag for a portion based on the access count for the portion. The controller issues an RFM command after checking the RFM flag if the RFM flag is set.

Inventors

• Randall J. Rooney
• Jeremy Chritz

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260505

Application Date

20240618

Claims (20)

1. 1 . An apparatus comprising: a memory array including: a first portion comprising a first plurality of word lines; a second portion comprising a second plurality of word lines; a mode register comprising a first refresh management (RFM) flag associated with the first portion and a second RFM flag associated with the second portion; a first refresh control circuit configured to set the first RFM flag based on a first plurality of count values, each associated with one of the first plurality of word lines; and a second refresh control circuit configured to set the second RFM flag based on a second plurality of count values, each associated with one of the second plurality of word lines, wherein the first refresh control circuit is configured to set the first RFM flag if the first aggressor queue includes at least one address and wherein the second refresh control circuit is configured to set the second RFM flag if the second aggressor queue includes at least one address.
2. 2 . The apparatus of claim 1 , wherein the mode register is configured to provide a status of the first RFM flag while accessing the second portion of the memory array.
3. 3 . The apparatus of claim 1 , wherein the first portion is a first bank and the second portion is a second bank.
4. 4 . The apparatus of claim 1 , wherein the first portion is a first sub-bank and the second portion is a second sub-bank.
5. 5 . The apparatus of claim 1 , wherein the first plurality of word lines is configured to store the first plurality of count values, and wherein the second plurality of word lines is configured to store the second plurality of count values.
6. 6 . The apparatus of claim 1 , wherein the first refresh control circuit includes a first aggressor queue configured to store aggressor addresses based on the first plurality of count values, and wherein the second refresh control circuit includes a second aggressor queue configured to store aggressor addresses based on the second plurality of count values.
7. 7 . The apparatus of claim 1 , wherein the first refresh control circuit is configured to perform a targeted refresh operation responsive to an RFM command directed to the first portion, and wherein the second refresh control circuit is configured to perform a targeted refresh operation responsive to an RFM command directed to the second portion.
8. 8 . The apparatus of claim 1 , wherein the first refresh control circuit is configured to set the first RFM flag if at least one of the first plurality of count values is above a threshold and to unset the first RFM flag if none of the first plurality of count values is above the threshold, and wherein the second refresh control circuit is configured to set the second RFM flag if at least one of the second plurality of count values is above the threshold and to unset the second RFM flag if none of the second plurality of count values is above the threshold.
9. 9 . The apparatus of claim 1 , wherein the first refresh control circuit is configured to change a selected one of the first count values responsive to the associated one of the first plurality of word lines being accessed, and wherein the second refresh control circuit is configured to change a selected one of the second count values responsive to the associated one of the second plurality of word lines being accessed.
10. 10 . A system comprising: a memory comprising: a memory array comprising a plurality of portions, each of the plurality of portions comprising a respective plurality of word lines each associated with a respective one of a plurality of count values; a mode register comprising a plurality of refresh management flags, each associated with one of the plurality of portions; and a plurality of refresh control circuits configured to set or unset the plurality of RFM flags based on the plurality of count values associated with the one of the plurality of portions associated with the RFM flag; and a controller configured to count a number of access operations to each of the plurality of portions, check the associated one of the plurality of RFM flags based on the count value and provide an RFM command to the memory if the checked associated one of the plurality of RFM flags is set.
11. 11 . The system of claim 10 , wherein the plurality of refresh control circuits are configured to set the associated one of the plurality of RFM flags if any of the associated plurality of count values is above a threshold and to unset the associated one of the plurality of RFM flags if none of the associated plurality of count values is above the threshold.
12. 12 . The system of claim 10 , wherein the plurality of refresh control circuits are configured to change a value of a selected one of the associated plurality of count values responsive to a selected one of the associated plurality of word lines being accessed.
13. 13 . The system of claim 10 , wherein the controller is configured to check the associated one of the plurality of RFM flags responsive to the number of access operations crossing a threshold.
14. 14 . The system of claim 10 , wherein the controller is configured to check the associated one of the plurality of RFM flags by performing a mode register read operation on the memory.
15. 15 . The system of claim 14 , wherein the controller is configured to perform an access operation on a different portion of the memory while performing the mode register read operation.
16. 16 . A method comprising: performing an access operation with a controller on a selected word line in a portion of a memory array of a memory; changing a first count value in the memory responsive to performing the access operation on the selected word line, wherein the first count value is associated with the selected word line; setting a refresh management (RFM) flag in the memory if the first count value crosses a first threshold; changing a second count value in the controller responsive to performing the access operation on the portion, wherein the second count value is associated with the portion; checking a status of the RFM flag if the second count value has crossed a second threshold; and issuing an RFM command to the memory if the RFM flag is set.
17. 17 . The method of claim 16 , further comprising: providing address information from the controller to the memory, wherein the address information specifies the portion of the memory array; and changing the second count value responsive to the address information.
18. 18 . The method of claim 16 , further comprising incrementing the first count value responsive to performing the access operation on the word line; and incrementing the second count value responsive to performing the access operation on the portion.
19. 19 . The method of claim 16 , further comprising storing a row address in an aggressor queue responsive to the first count value crossing the first threshold.
20. 20 . The method of claim 16 , wherein checking the status of the RFM flag includes performing a mode register read (MRR) operation on a mode register of the memory.

Description

CROSS REFERENCE TO RELATED APPLICATION(S) This application claims the benefit under 35 U.S.C. § 119 of the earlier filing date of U.S. Provisional Application Ser. No. 63/588,789 filed Oct. 9, 2023 the entire contents of which is hereby incorporated by reference in its entirety for any purpose. BACKGROUND Information may be stored on memory cells of a memory device. The memory cells may be organized at the intersection of word lines (rows) and bit lines (columns). Information in the memory cells may decay over time. For example, the information may be stored as a charge on a capacitor which may decay over time. The memory device may perform refresh operations to restore the information and prevent information from being lost. Certain patterns of access may cause an increased rate of information decay in nearby memory cells (e.g., the memory cells along nearby word lines). Memory devices may use various schemes to identify these access patterns so that additional targeted refresh operations may be performed. A controller may signal the memory to perform refresh operations, some of which may be sequential operations to refresh memory cells decaying at an expected rate and some of which may be targeted refresh operations. However, refresh operations may take up time which could be used for other operations, and may use power. There may be a need to ensure that the controller does not over issue refresh commands. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a memory system according to some embodiments of the present disclosure. FIG. 2 is a block diagram of a semiconductor device according to at least one embodiment of the disclosure. FIG. 3 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. FIG. 4 is a block diagram of a controller according to some embodiments of the present disclosure. FIG. 5 is a flow chart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the disclosure or its applications or uses. In the following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings which form a part hereof, and which are shown by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the disclosure. Moreover, for the purpose of clarity, detailed descriptions of certain features will not be discussed when they would be apparent to those with skill in the art so as not to obscure the description of embodiments of the disclosure. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the disclosure is defined only by the appended claims. Information in a memory array may be accessed by one or more access operations, such as read or write operations. During an example access operation a word line may be activated based on a row address and then selected memory cells along that active word line may have their information read or written to based on which bit lines are accessed, which may be based on a column address. The memory array may be refreshed on a row by row basis (e.g., as part of an auto-refresh and/or self-refresh mode) where the memory cells along each row are refreshed periodically. Such refresh operations may be referred to as sequential refresh operations or normal refresh operations, as the memory may use some sequence logic (e.g., a counter) to generate the refresh addresses. The speed at which the rows are refreshed (e.g., the maximum time any given row will go between refreshes) may be determined based on an expected rate of information decay and may be adjusted based on various conditions of the memory (e.g., temperature). Various patterns of access to a row (an aggressor row) may cause an increased rate of information decay in nearby memory cells (e.g., along victim rows). For example, a ‘row hammer’ may involve repeated accesses to the aggressor row which may increase a rate of decay in adjacent rows (and/or in rows which are further away). Accordingly, it may be important to track a number of accesses to each row to determine if they are aggressors, such that the victim rows can be identified and refreshed as part of a targeted refresh operation. For example, each word line may have an associated count value which is used to determine how many times that word line has been accessed. The memory device may monitor accesses to word lines to determine if they are aggressors or not (e.g., if the number of accesses cross