US-12620431-B2 - Refresh management selection

Abstract

Refresh management commands are issued to a memory device in order to cause the refresh of rows in the vicinity of one or more rows being “hammered.” These refresh management commands are each associated with respective row addresses that indicates the row(s) to be refreshed in order to mitigate the likelihood of data being corrupted by “row hammer.” In an embodiment, the refresh management commands are issued in response to a varying number of activate (ACT) commands having been issued since the last refresh management command. The row selected for a given refresh management command may be selected based on rows that have recently been activated. The selection may be based on “pools” of recently activated rows where these pools are of unequal size. The selection from a given pool may be based on algorithmic and/or random techniques.

Inventors

• Steven C. Woo
• Taeksang Song

Assignees

• RAMBUS INC.

Dates

Publication Date

20260505

Application Date

20230314

Claims (20)

1. 1 . A memory controller, comprising: an external command interface to transmit row activate (ACT) commands and refresh management (RFM) commands to an external memory device; and, control circuitry to determine a first number of row activate commands to be transmitted between a first refresh management command and a second refresh management command, and to determine a second number of row activate commands to be transmitted between the second refresh management command and a third refresh management command, the first number and the second number to be unequal, the first, second, and third refresh management commands to respectively cause a refresh of rows physically adjacent to respective selected rows of the external memory device, wherein the first number and the second number are positive integers.
2. 2 . The memory controller of claim 1 , wherein the memory controller receives, from the external memory device, a first indicator associated with a third number of row activate commands.
3. 3 . The memory controller of claim 2 , wherein the first number is greater than the third number and the second number is less than the third number.
4. 4 . The memory controller of claim 2 , wherein an average of the first number and the second number is not equal to the third number.
5. 5 . The memory controller of claim 2 , wherein the memory controller selects a first row address from a first plurality of row addresses transmitted in association with a first plurality of row activate commands transmitted to the external memory device between the first refresh management command and the second refresh management command and, transmits the second refresh management command to the external memory device in association with the first row address.
6. 6 . The memory controller of claim 5 , wherein the memory controller selects a third row address from a second plurality of row addresses transmitted in association with a second plurality of row activate commands transmitted to the external memory device between the second refresh management command and the third refresh management command and, transmits the third refresh management command to the external memory device in association with the second row address.
7. 7 . The memory controller of claim 5 , wherein a first row addressed by the first row address is physically adjacent to a second row addressed by the second row address.
8. 8 . A memory controller, comprising: an external command interface to transmit, to an external memory device, a first number of row activate (ACT) commands between a first pair of consecutive refresh management commands, and to transmit a second number of row activate commands between a second pair of consecutive refresh management commands, wherein refresh management commands are to respectively cause a refresh of rows physically adjacent to respective selected rows of the external memory device; and wherein the first number and the second number are not equal, and wherein the first number and the second number are positive integers.
9. 9 . The memory controller of claim 8 , wherein the external command interface is to also transmit a third number of row activate commands between a third pair of consecutive refresh management commands, the third number is not equal to the first number and is not equal to the second number, and the third number is a positive integer.
10. 10 . The memory controller of claim 8 , wherein the external memory device selects is to select a first row address from a first plurality of row addresses transmitted by the external command interface to the external memory device between the first pair of consecutive refresh management commands and, in response to a first refresh management command and based on the first row address, the external memory device selects at least a second row address to be refreshed.
11. 11 . The memory controller of claim 10 , wherein the external memory device uses a randomized selection technique to select the first row address from the first plurality of row addresses.
12. 12 . The memory controller of claim 11 , wherein a first row addressed by the first row address is physically adjacent to a second row addressed by the second row address.
13. 13 . The memory controller of claim 11 , wherein the external memory device uses the randomized selection technique to select a third row address from a second plurality of row addresses transmitted by the external command interface to the external memory device between the second pair of consecutive refresh management commands.
14. 14 . The memory controller of claim 8 , wherein the first pair of consecutive refresh management commands and the second pair of consecutive refresh management commands are to have a common refresh management command.
15. 15 . A method of operating a memory device, comprising: transmitting, to an external command interface of the memory device, a first number of row activate commands between a first pair of consecutive refresh management commands; and transmitting, to the external command interface of the memory device, a second number of row activate commands between a second pair of consecutive refresh management commands, wherein the first number and the second number are not equal, the first number and the second number are positive integers, and the consecutive refresh management commands are to respectively cause a refresh of rows physically adjacent to respective selected rows of the memory device.
16. 16 . The method of claim 15 , further comprising: transmitting, to the external command interface of the memory device, a third number of row activate commands between a third pair of consecutive refresh management commands, wherein the third number is a positive integer, is not equal to the first number, and is not equal to the second number.
17. 17 . The method of claim 15 , further comprising: receiving, from the memory device, an indicator of a selected number of row activate commands to be transmitted to the external command interface of the memory device between pairs of consecutive refresh management commands.
18. 18 . The method of claim 17 , wherein the selected number is not equal to the first number and is not equal to the second number.
19. 19 . The method of claim 18 , wherein a sum of the first number and the second number is less than or equal to the selected number.
20. 20 . The method of claim 15 , wherein the memory device, in response to receiving a refresh management command, is to refresh a first row that is physically adjacent to a second row, where an address of the second row was transmitted, to the external command interface of the memory device, between the first pair of consecutive refresh management commands.

Description

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a memory system with memory device refresh management selection. FIG. 2 is a block diagram illustrating a memory system with memory controller refresh management selection. FIG. 3 is a block diagram illustrating a memory system with memory controller row address tracking. FIG. 4 is a block diagram illustrating a memory system with registering clock driver refresh management selection. FIGS. 5A-5B are diagrams illustrating refresh management command occurrence. FIGS. 6A-6B are diagrams illustrating refresh management row selection. FIG. 7 is a flowchart illustrating a method of issuing refresh management commands. FIG. 8 is a flowchart illustrating a method of selecting refresh management command occurrences. FIG. 9 is flowchart illustrating a method of selecting refresh management command row addresses. FIG. 10 is a flowchart illustrating a method of issuing refresh management commands and associated rows. FIG. 11 is a diagram illustrating refresh management commands with rows selected from a plurality of pools. FIG. 12 is a flowchart illustrating a method of issuing refresh management commands and associated rows. FIG. 13 is a diagram illustrating refresh management commands with rows selected from a plurality of pools organized into a plurality of pool groups. FIG. 14 is a block diagram illustrating a processing system. DETAILED DESCRIPTION OF THE EMBODIMENTS Repeated row activations of the same row in a dynamic random access memory (DRAM) device (whether malicious or accidental) can cause cells in the neighborhood of the repeatedly activated row to lose a stored value. This effect on DRAM storage reliability has been termed “row hammer.” Row hammer, when applied to the multiple, parallel, DRAM device accesses that may occur with memory modules, can cause multiple errors across multiple DRAM devices on the module that are possibly uncorrectable and/or undetectable. In an embodiment, refresh management (RFM) commands are issued to a memory device in order to cause the refresh of rows in the vicinity of one or more rows being “hammered.” These refresh management commands are each associated with respective row addresses that indicates the row(s) to be refreshed in order to mitigate the likelihood of data being corrupted by “row hammer.” In an embodiment, these associations may be specified as part of the refresh management commands. In other embodiments, these associations may be made by a device (e.g., memory device, or registering clock driver) that receives the activate (ACT) and refresh management commands. In an embodiment, the refresh management commands are issued in response to a varying number of activate commands having been issued since the last refresh management command. In other words, for example, rather than issuing a refresh management command for every 32 activate commands, the memory system may alternate between issuing a refresh management command after 61 activates and 3 activates. In this example, the average rate of a refresh management command for every 32 activates (i.e., 61+3=64 and 64/2=32) is maintained. In an embodiment, the row selected for a given refresh management command may be selected based on rows that have recently been activated (e.g., since last one or two RFM commands). The selection may also be based on “pools” of recently activated rows where these pools are of unequal size. The selection from a given pool may be based on algorithmic (e.g., first activate placed in the pool after an RFM command) and/or random techniques (e.g., selecting one activate at random from a pool). The descriptions and embodiments disclosed herein may be made with references to DRAM devices and DRAM memory arrays. This, however, should be understood to be a first example where, due at least to the widespread adoption of DRAM technology, “row-hammer” has been observed and studied. It should be understood that other memory technologies that may be susceptible to “row-hammer” and therefore may also benefit from the methods and/or apparatus described herein. These memory technologies include, but are not limited to static random access memory (SRAM), non-volatile memory (such as flash), conductive bridging random access memory (CBRAM—a.k.a., programmable metallization cell—PMC), resistive random access memory (a.k.a., RRAM or ReRAM), magnetoresistive random-access memory (MRAM), Spin-Torque Transfer (STT-MRAM), phase change memory (PCM), and the like, and/or combinations thereof. Accordingly, it should be understood that in the disclosures and/or descriptions given herein, these aforementioned technologies may be substituted for, included with, and/or encompassed within, the references to DRAM, DRAM devices, and/or DRAM arrays made herein. FIG. 1 is a block diagram illustrating a memory system with memory device refresh management selection. In FIG. 1, memory system 100 comprises memory device 110 and memory controller 120