US-12620432-B2 - Delay adjuster based clock qualifier timing enhancement for memory interface

Abstract

A method for operating a memory interface circuit includes generating an internal data strobe signal based on a first data strobe signal and a second data strobe signal using a first receiver, generating a qualifier signal based on the second data strobe signal and a reference voltage using a second receiver, delaying a rise time and a fall time of the qualifier signal using a delay adjuster, generating a gate control signal based on the internal data strobe signal and the qualifier signal after the delay adjuster, and gating a portion of the internal data strobe signal based on the gate control signal to provide a read clock signal.

Inventors

• Satish Krishnamoorthy
• Yong Xu
• Boris Dimitrov Andreev
• Patrick Isakanian
• Farrukh Aquil

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260505

Application Date

20240212

Claims (17)

1. 1 . A memory interface circuit, comprising: a first receiver having a first input, a second input, and an output, wherein the first input of the first receiver is configured to receive a first data strobe signal, and the second input of the first receiver is configured to receive a second data strobe signal; a second receiver having a first input, a second input, and an output, wherein the first input of the second receiver is configured to receive the second data strobe signal, and the second input of the second receiver is configured to receive a first reference voltage; a gating circuit having a first input, a second input, and an output, wherein the first input of the gating circuit is coupled to the output of the first receiver; a gate control circuit having a first input, a second input, and an output, wherein the second input of the gate control circuit is coupled to the output of the first receiver, and the output of the gate control circuit is coupled to the second input of the gating circuit; a delay adjuster coupled between the output of the second receiver and the first input of the gate control circuit; a first bias current source configured to provide a first bias current for the first receiver; and a second bias current source configured to provide a second bias current for the second receiver, wherein the first bias current and the second bias current are different.
2. 2 . The memory interface circuit of claim 1 , wherein the delay adjuster has a rise time delay and a fall time delay, and the rise time delay and the fall time delay are different.
3. 3 . The memory interface circuit of claim 2 , wherein the delay adjuster is configured to independently tune the rise time delay and the fall time delay.
4. 4 . The memory interface circuit of claim 2 , wherein the delay adjuster is configured to receive a rise code and a fall code, set the rise time delay based on the rise code, and set the fall time delay based on the fall code.
5. 5 . The memory interface circuit of claim 1 , wherein the gate control circuit comprises: a qualifier flip-flop having a clock input, a signal input, and an output, wherein the clock input of the qualifier flip-flop is coupled to the first input of the gate control circuit, and the signal input of the qualifier flip-flop is coupled to a logic value; and one or more strobe flip-flops coupled in series between the output of the qualifier flip-flop and the output of the gate control circuit, wherein each of the one or more strobe flip-flops has a respective clock input coupled to the second input of the gating circuit.
6. 6 . The memory interface circuit of claim 1 , further comprising a receiver control circuit coupled to the first receiver and the second receiver, wherein the receiver control circuit is configured to independently tune a delay of the first receiver and a delay of the second receiver.
7. 7 . The memory interface circuit of claim 1 , wherein the second bias current is greater than the first bias current.
8. 8 . The memory interface circuit of claim 1 , further comprising a duty-cycle monitor configured to detect a duty cycle of a qualifier signal between the delay adjuster and the first input of the gate control circuit.
9. 9 . The memory interface circuit of claim 8 , further comprising a delay control circuit coupled to the duty-cycle monitor, wherein the duty-cycle monitor is configured to output a signal indicating the detected duty cycle, and wherein the delay control circuit is configured to receive the signal indicating the detected duty cycle, and tune a rise time delay or a fall time delay of the delay adjuster based on the signal indicating the detected duty cycle.
10. 10 . The memory interface circuit of claim 1 , further comprising a delay control circuit coupled to the delay adjuster, wherein the delay control circuit is configured to: sweep a fall time delay or a rise time delay of the delay adjuster to different delay settings; for each of the delay settings, determine whether one or more timing requirements in the memory interface circuit are met; and select one of the delay settings meeting the one or more timing requirements.
11. 11 . A memory interface circuit, comprising: a first receiver having a first input, a second input, and an output, wherein the first input of the first receiver is configured to receive a first data strobe signal, and the second input of the first receiver is configured to receive a second data strobe signal; a second receiver having a first input, a second input, and an output, wherein the first input of the second receiver is configured to receive the second data strobe signal, and the second input of the second receiver is configured to receive a first reference voltage; a gating circuit having a first input, a second input, and an output, wherein the first input of the gating circuit is coupled to the output of the first receiver; a gate control circuit having a first input, a second input, and an output, wherein the second input of the gate control circuit is coupled to the output of the first receiver, and the output of the gate control circuit is coupled to the second input of the gating circuit; a delay adjuster coupled between the output of the second receiver and the first input of the gate control circuit; a third receiver having a first input, a second input, and an output, wherein the first input of the third receiver is configured to receive a data signal, and the second input of the third receiver is configured to receive a second reference voltage; and a data capture circuit having a data input, a clock input, and an output, wherein the data input of the data capture circuit is coupled to the output of the third receiver, and the clock input of the data capture circuit is coupled to the output of the gating circuit.
12. 12 . The memory interface circuit of claim 11 , further comprising a calibrated delay circuit coupled between the output of the gating circuit and the clock input of the data capture circuit.
13. 13 . The memory interface circuit of claim 11 , further comprising a duty-cycle corrector coupled between the output of the third receiver and the data input of the data capture circuit.
14. 14 . A method for operating a memory interface circuit, comprising: generating an internal data strobe signal based on a first data strobe signal and a second data strobe signal using a first receiver; generating a qualifier signal based on the second data strobe signal and a reference voltage using a second receiver; delaying a rise time and a fall time of the qualifier signal using a delay adjuster; generating a gate control signal based on the internal data strobe signal and the qualifier signal after the delay adjuster; and gating a portion of the internal data strobe signal based on the gate control signal to provide a read clock signal, wherein generating the gate control signal comprises propagating the gate control signal through a qualifier flip-flop and one or more strobe flip-flops, wherein the qualifier flip-flop is clocked by the qualifier signal after the delay adjuster, and each of the one or more strobe flip-flops is clocked by the internal data strobe signal.
15. 15 . The method of claim 14 , further comprising: receiving a data signal; and capturing data bits from the data signal on rising edges and falling edges of the read clock signal.
16. 16 . The method of claim 15 , wherein the portion of the internal data strobe signal comprises a preamble of the internal data strobe signal.
17. 17 . The method of claim 14 , wherein a rise time delay and a fall time delay of the delay adjuster are different.

Description

BACKGROUND Field Aspects of the present disclosure relate generally to memory, and more particularly, to memory interface circuits. Background A mobile device may include one or more processors and one or more memory devices for storing data and/or instructions for the one or more processors. For example, the one or more memory devices may be implemented with synchronous dynamic random-access memory (SDRAM) such as low-power double data rate (LPDDR) SDRAM. The one or more processors may access the one or more memory devices using a memory controller, which interfaces with the one or more memory devices via a memory interface circuit. SUMMARY The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later. A first aspect relates to a memory interface circuit. The memory interface circuit includes a first receiver having a first input, a second input, and an output, wherein the first input of the first receiver is configured to receive a first data strobe signal, and the second input of the first receiver is configured to receive a second data strobe signal. The memory interface circuit also includes a second receiver having a first input, a second input, and an output, wherein the first input of the second receiver is configured to receive the second data strobe signal, and the second input of the second receiver is configured to receive a first reference voltage. The memory interface circuit also includes a gating circuit having a first input, a second input, and an output, wherein the first input of the gating circuit is coupled to the output of the first receiver. The memory interface circuit also includes a gate control circuit having a first input, a second input, and an output, wherein the second input of the gate control circuit is coupled to the output of the first receiver, and the output of the gate control circuit is coupled to the second input of the gating circuit. The memory interface circuit further includes a delay adjuster coupled between the output of the second receiver and the first input of the gate control circuit. A second aspect relates to a method for operating a memory interface circuit. The method includes generating an internal data strobe signal based on a first data strobe signal and a second data strobe signal using a first receiver, generating a qualifier signal based on the second data strobe signal and a reference voltage using a second receiver, delaying a rise time and a fall time of the qualifier signal using a delay adjuster, generating a gate control signal based on the internal data strobe signal and the qualifier signal after the delay adjuster, and gating a portion of the internal data strobe signal based on the gate control signal to provide a read clock signal. A third aspect relates to a method for training a delay adjuster in a memory interface circuit. The memory interface circuit includes a first receiver, a gating circuit coupled to the first receiver, a gate control circuit coupled to the gating circuit, and a second receiver, wherein the delay adjuster is coupled between the second receiver and the gate control circuit. The method includes sweeping a fall time delay or a rise time delay of the delay adjuster to different delay settings. The method also includes, for each of the delay settings, determining whether one or more timing requirements in the memory interface circuit are met. The method further includes selecting one of the delay settings meeting the one or more timing requirements. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A shows an example of a system including a processor, a memory controller, a memory interface circuit, and a memory device according to certain aspects of the present disclosure. FIG. 1B shows an example in which the processor and the memory controller are integrated on a chip and the memory device is external to the chip according to certain aspects of the present disclosure. FIG. 2 shows an exemplary implementation of a memory interface circuit according to certain aspects of the present disclosure. FIG. 3A shows an example of a reference voltage source providing a reference voltage in the memory interface circuit of FIG. 2 according to certain aspects of the present disclosure. FIG. 3B shows an example of a first reference voltage source providing a first reference voltage and a second reference voltage source providing a second reference voltage in the memory interface circuit of FIG. 2 according to certain aspects of the present disclosure. FIG. 4A shows an exemplary implem