US-12620434-B2 - Time-varying threshold for usage-based disturbance mitigation

US12620434B2US 12620434 B2US12620434 B2US 12620434B2US-12620434-B2

Abstract

Apparatuses and techniques for implementing aspects of a time-varying threshold for usage-based disturbance mitigation. In an example aspect, usage-based disturbance circuitry of a memory device utilizes a threshold that varies over time for detecting conditions associated with usage-based disturbance. By utilizing the time-varying threshold, the usage-based disturbance circuitry can reduce a probability of a waterfall event causing a denial-of-service (DOS) situation. In particular, the time-varying threshold can spread out the refreshing of rows over a longer time period. This enables the memory device to have sufficient resources to service other memory requests while also mitigating usage-based disturbance. In example implementations, the threshold is at least partially randomized, which can make it challenging for a malicious actor to identify and overcome the usage-based disturbance mitigation techniques. Also, techniques for generating the time-varying threshold can be implemented without appreciably increasing a size or cost of the memory device.

Inventors

Yang Lu
Yuan He
Kang-Yong Kim

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260505
Application Date: 20240509

Claims (20)

1 . An apparatus comprising: a memory device comprising: a memory array configured to store an activation count that represents a quantity of times a row within the memory array has been activated; and circuitry that is coupled to the memory array and configured to detect a condition associated with usage-based disturbance based on the activation count being greater than or equal to a threshold, the threshold being at least partially randomized such that a value of the threshold varies over time.
2 . The apparatus of claim 1 , wherein the circuitry is configured to select the threshold from a table of values.
3 . The apparatus of claim 1 , wherein the circuitry is configured to generate the threshold based on a fixed component and a time-varying component.
4 . The apparatus of claim 3 , wherein the circuitry comprises: at least one register configured to store a value associated with the fixed component; and at least one linear-feedback shift register or at least one sequencer configured to generate the time-varying component.
5 . The apparatus of claim 3 , wherein the fixed component represents a larger portion of the threshold than the time-varying component.
6 . The apparatus of claim 5 , wherein: the threshold comprises: an upper portion comprising at least a most-significant bit; and a lower portion comprising at least a least-significant bit; and the circuitry comprises a multiplexer configured to combine the fixed component and the time-varying component such that the fixed component represents the upper portion of the threshold and the time-varying component represents the lower portion of the threshold.
7 . The apparatus of claim 5 , wherein: the fixed component represents a first positive integer; the circuitry is configured to generate the time-varying component having a value between zero and a second positive integer, the second positive integer being less than the first positive integer; and the circuitry comprises a summation circuit configured to add the fixed component and the time-varying component to generate the threshold.
8 . The apparatus of claim 1 , wherein the memory array comprises multiple rows respectively configured to store multiple activation counts corresponding to the multiple rows.
9 . A method comprising: storing, by a memory array, an activation count that represents a quantity of times a row within the memory array has been activated; generating, by circuitry, a threshold that is at least partially randomized such that a value of the threshold varies over time; and detecting, by the circuitry, a condition associated with usage-based disturbance based on the activation count being greater than or equal to the threshold.
10 . The method of claim 9 , wherein: the generating of the threshold comprises generating the threshold based on a fixed component and a time-varying component; and the fixed component represents a larger portion of the threshold than the time-varying component.
11 . The method of claim 10 , wherein the threshold comprises: an upper portion comprising at least a most-significant bit; and a lower portion comprising at least a least-significant bit; and the generating of the threshold comprises combining the fixed component and the time-varying component such that the fixed component represents the upper portion of the threshold and the time-varying component represents the lower portion of the threshold.
12 . The method of claim 10 , wherein the generating of the threshold comprises: generating the fixed component to have a value equal to a first positive integer; generating the time-varying component to have a value between zero and a second positive integer that is less than the first positive integer; and adding the fixed component and the time-varying component to generate the threshold.
13 . The method of claim 9 , further comprising: storing, by the memory array, a second activation count that represents a quantity of times a second row within the memory array has been activated; and detecting, by the circuitry, a condition associated with the usage-based disturbance based on the second activation count being greater than or equal to the threshold.
14 . The method of claim 13 , wherein: the generating of the threshold comprises generating the threshold to have a first value; and the method further comprises: prior to detecting the condition associated with the usage-based disturbance based on the second activation count being greater than or equal to the threshold, updating the threshold to have a second value that differs from the first value.
15 . The method of claim 14 , further comprising: activating, by a memory device, multiple rows within the memory array, the multiple rows including the row and the second row, wherein the updating of the threshold comprises updating the threshold responsive to a quantity of activations since the generating of the threshold being greater than or equal to a threshold.
16 . The method of claim 14 , further comprising: starting a timer responsive to the generating of the threshold, wherein the updating of the threshold comprises updating the threshold responsive to an expiration of the timer.
17 . An apparatus comprising: a memory device comprising: a threshold generator configured to generate a threshold that is at least partially randomized such that a value of the threshold varies over time; a counter circuit configured to increment an activation count associated with a row that is activated within a memory array of the memory device; and a comparator circuit coupled to the threshold generator and the counter circuit, the comparator circuit configured to compare the activation count to the threshold to detect a condition associated with usage-based disturbance.
18 . The apparatus of claim 17 , wherein: the threshold generator is configured to generate the threshold based on a fixed component and a time-varying component; and the fixed component represents a larger portion of the threshold than the time-varying component.
19 . The apparatus of claim 18 , wherein the threshold generator comprises: at least one register configured to store a value associated with the fixed component; and at least one random number generator configured to generate the time-varying component.
20 . The apparatus of claim 19 , wherein: the threshold generator comprises a combiner circuit having: inputs respectively coupled to the at least one register and the random number generator; and an output coupled to the comparator circuit; and the combiner circuit comprises a multiplexer or a summation circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims the benefit of U.S. Provisional Patent Application Ser. No. 63/501,895 filed on May 12, 2023, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND Computers, smartphones, and other electronic devices rely on processors and memories. A processor executes code based on data to run applications and provide features to a user. The processor obtains the code and the data from a memory. The memory in an electronic device can include volatile memory (e.g., random-access memory (RAM)) and non-volatile memory (e.g., flash memory). Like the capabilities of a processor, the capabilities of a memory can impact the performance of an electronic device. This performance impact can increase as processors are developed that execute code faster and as applications operate on increasingly larger data sets that require ever-larger memories. BRIEF DESCRIPTION OF THE DRAWINGS Apparatuses of and techniques for implementing aspects of a time-varying threshold for usage-based disturbance mitigation are described with reference to the following drawings. The same numbers are used throughout the drawings to reference like features and components: FIG. 1 illustrates example apparatuses that can implement aspects of a time-varying threshold for usage-based disturbance mitigation; FIG. 2 illustrates an example computing system that can implement aspects of a time-varying threshold for usage-based disturbance mitigation; FIG. 3 illustrates an example memory device in which aspects of a time-varying threshold for usage-based disturbance may be implemented; FIG. 4 illustrates example components of usage-based disturbance circuitry that can implement aspects of a time-varying threshold for usage-based disturbance mitigation; FIG. 5 illustrates an example implementation of a threshold generator that can generate a time-varying threshold for usage-based disturbance mitigation; FIG. 6 illustrates an example flow diagram for performing aspects of generating a time-varying threshold for usage-based disturbance mitigation; FIG. 7 illustrates another example flow diagram for performing aspects of generating a time-varying threshold for usage-based disturbance mitigation; and FIG. 8 illustrates an example method for a memory device performing aspects of generating a time-varying threshold for usage-based disturbance mitigation. DETAILED DESCRIPTION Overview Processors and memory work in tandem to provide features to users of computers and other electronic devices. As processors and memory operate more quickly together in a complementary manner, an electronic device can provide enhanced features, such as high-resolution graphics and artificial intelligence (AI) analysis. Some applications, such as those for financial services, medical devices, and advanced driver assistance systems (ADAS), can also demand more-reliable memories. These applications use increasingly reliable memories to limit errors in financial transactions, medical decisions, and object identification. However, in some implementations, more-reliable memories can sacrifice bit densities, power efficiency, and simplicity. To meet the demands for physically smaller memories, memory devices can be designed with higher chip densities. Increasing chip density, however, can increase the electromagnetic coupling (e.g., capacitive coupling) between adjacent or proximate rows of memory cells due, at least in part, to a shrinking distance between these rows. With this undesired coupling, activation (or charging) of a first row of memory cells can sometimes negatively impact a second nearby row of memory cells. In particular, activation of the first row can generate interference, or crosstalk, that causes the second row to experience a voltage fluctuation. In some instances, this voltage fluctuation can cause a state (or value) of a memory cell in the second row to be incorrectly determined by a sense amplifier. Consider an example in which a state of a memory cell in the second row is a “1”. In this example, the voltage fluctuation can cause a sense amplifier to incorrectly determine the state of the memory cell to be a “0” instead of a “1”. Left unchecked, this interference can lead to memory errors or data loss within the memory device. In some circumstances, a particular row of memory cells is activated repeatedly in an unintentional or intentional (sometimes malicious) manner. Consider, for instance, that memory cells in an Rth row are subjected to repeated activation, which causes one or more memory cells in an adjacent row (e.g., within an R+1 row, an R+2 row, an R−1 row, and/or an R−2 row) to change states. This effect is referred to as usage-based disturbance. The occurrence of usage-based disturbance can lead to the corruption or changing of contents within the affected row of memory. Some memory devices monitor how often a row of memory cells is activated and refresh nearby rows to mi