US-12620435-B2 - Semiconductor system for inputting and outputting data

Abstract

A data input and output circuit includes a data input circuit configured to precharge first and second input and output lines after the end of a power-up operation and configured to generate first and second input data by driving the first and second input and output lines from each of which transfer data having a set logic level, among first and second transfer data, are output after the start of a write operation. The data input and output circuit also includes a data output circuit configured to generate first and second internal data based on logic levels of the first and second input data.

Inventors

• Hyun Seung Kim

Assignees

• SK Hynix Inc.

Dates

Publication Date

20260505

Application Date

20231003

Priority Date

20230615

Claims (20)

1. 1 . A semiconductor system comprising: a controller configured to drive first and second transmission lines to a first logic level after a start of an initialization operation and configured to output first and second data by driving the first and second transmission lines from each of which pre-data having a second logic level, among first and second pre-data, are output after a start of a write operation; and a semiconductor device configured to drive first and second input and output lines to the first logic level after an end of a power-up operation, configured to generate first and second internal data by driving the first and second input and output lines from each of which transfer data having the second logic level, among first and second transfer data that are generated from the first and second data, are output after the start of the write operation, and configured to store the first and second internal data.
2. 2 . The semiconductor system of claim 1 , wherein the controller comprises: a first transmitter configured to drive the first transmission line to the first logic level after the start of the initialization operation and configured to generate the first data by driving the first transmission line to the second logic level when the first pre-data has the second logic level after the start of the write operation; and a second transmitter configured to drive the second transmission line to the first logic level after the start of the initialization operation and configured to generate the second data by driving the second transmission line to the second logic level when the second pre-data has the second logic level after the start of the write operation.
3. 3 . The semiconductor system of claim 1 , wherein the controller comprises: a first transmitter configured to drive the first transmission line to the first logic level after the start of the initialization operation and configured to generate the first data by driving the first transmission line to the first logic level when the first pre-data has the first logic level after the start of the write operation; and a second transmitter configured to drive the second transmission line to the first logic level after the start of the initialization operation and configured to generate the second data by driving the second transmission line to the first logic level when the second pre-data has the first logic level after the start of the write operation.
4. 4 . The semiconductor system of claim 1 , wherein logic levels of the first and second pre-data transition at a same time, and the first and second pre-data are input in parallel.
5. 5 . The semiconductor system of claim 1 , wherein the semiconductor device comprises: a reception circuit configured to generate the first and second transfer data by receiving the first and second data after the start of the write operation; a data input and output circuit configured to drive the first and second input and output lines to the first logic level after the end of the power-up operation and configured to generate the first and second internal data by driving the first and second input and output lines from each of which transfer data having the second logic level, among the first and second transfer data, are output after the start of the write operation; and a memory circuit configured to store the first and second internal data in a memory cell that is selected based on an internal command and an internal address after the start of the write operation.
6. 6 . The semiconductor system of claim 5 , wherein the reception circuit comprises: a first receiver configured to generate the first transfer data by inverting and buffering the first data after the start of the write operation; and a second receiver configured to generate the second transfer data by inverting and buffering the second data after the start of the write operation.
7. 7 . The semiconductor system of claim 5 , wherein the data input and output circuit comprises: a data input circuit configured to drive the first and second input and output lines to the first logic level when a precharge signal is enabled and configured to generate the first and second internal data by driving the first and second input and output lines from each of which the transfer data having the second logic level, among the first and second transfer data, are output in synchronization with an internal strobe signal; and a data output circuit configured to generate the first and second internal data based on logic levels of the first and second input data.
8. 8 . The semiconductor system of claim 7 , wherein the data input circuit comprises: a first internal transmitter configured to drive the first input and output line to the first logic level when the precharge signal is enabled and configured to generate the first input data by driving the first input and output line to the second logic level when the first transfer data has the second logic level in synchronization with the internal strobe signal; and a second internal transmitter configured to drive the second input and output line to the first logic level when the precharge signal is enabled and configured to generate the second input data by driving the second input and output line to the second logic level when the second transfer data has the second logic level in synchronization with the internal strobe signal.
9. 9 . The semiconductor system of claim 7 , wherein the data output circuit comprises: a first internal receiver configured to generate the first internal data by driving a first node based on a logic level of the first input data; and a second internal receiver configured to generate the second internal data by driving a second node based on a logic level of the second input data.
10. 10 . The semiconductor system of claim 9 , wherein the first internal receiver comprises: a first pull-up driving element disposed between a power supply voltage and the first node and configured to drive the first node to a level of the power supply voltage when the first input data has the second logic level; and a first pull-down driving element disposed between the first node and a ground voltage and configured to drive the first node to a level of the ground voltage when the first input data has the first logic level.
11. 11 . The semiconductor system of claim 10 , wherein: the first pull-up driving element is further configured to generate the first internal data having the first logic level by driving the first node by first driving power when the first input data has the second logic level, and the first pull-down driving element is further configured to generate the first internal data having the second logic level by driving the first node by second driving power when the first input data has the first logic level.
12. 12 . The semiconductor system of claim 9 , wherein the second internal receiver comprises: a second pull-up driving element disposed between a power supply voltage and the second node and configured to drive the second node to a level of the power supply voltage when the second input data has the second logic level; and a second pull-down driving element disposed between the second node and a ground voltage and configured to drive the second node to a level of the ground voltage when the second input data has the first logic level.
13. 13 . The semiconductor system of claim 12 , wherein: the second pull-up driving element is further configured to generate the second internal data having the first logic level by driving the second node by first driving power when the second input data has the second logic level, and the second pull-down driving element is further configured to generate the second internal data having the second logic level by driving the second node by second driving power when the second input data has the first logic level.
14. 14 . The semiconductor system of claim 5 , further comprising: a command decoder configured to generate the internal command based on a command address in synchronization with a clock that is periodically toggled and configured to generate an internal strobe signal and a precharge signal that are enabled after the end of the power-up operation and after the start of the write operation; and an address decoder configured to generate the internal address based on the command address in synchronization with the clock.
15. 15 . The semiconductor system of claim 14 , wherein the command decoder comprises: an internal command generation circuit configured to generate the internal command that is enabled when the command address has a logic level combination for performing the write operation in synchronization with the clock; an internal strobe signal generation circuit configured to generate the internal strobe signal that is enabled after a time at which the internal command is enabled; and a precharge signal generation circuit configured to generate the precharge signal that is enabled when a reset signal is enabled and that is enabled when the internal strobe signal is disabled after the end of the power-up operation.
16. 16 . The semiconductor system of claim 15 , wherein the precharge signal generation circuit comprises: a pulse generation circuit configured to generate an internal pulse that is enabled at a time at which the internal strobe signal is disabled; and a logic circuit configured to generate the precharge signal that is enabled when any one of the reset signal and the internal pulse is enabled.
17. 17 . A semiconductor system comprising: a controller configured to output a clock and a command address and configured to output first and second data in series; and a semiconductor device configured to drive first and second input and output lines to a first logic level after an end of a power-up operation, configured to generate first and second alignment data by parallelizing first and second data based on the command address after a start of a write operation, configured to generate first and second internal data by driving the first and second input and output lines from each of which alignment data having a second logic level, among the first and second alignment data, are output, and configured to store the first and second internal data.
18. 18 . The semiconductor system of claim 17 , wherein the semiconductor device comprises: a data alignment circuit configured to sequentially latch the first and second data and configured to generate the first and second alignment data by aligning the latched first and second data; a data input circuit configured to drive the first and second input and output lines to the first logic level when a precharge signal is enabled and configured to generate the first and second internal data by driving the first and second input and output lines from each of which alignment data having the second logic level, among the first and second alignment data, are output in synchronization with an internal strobe signal that is generated the command address; and a data output circuit configured to generate the first and second internal data based on logic levels of the first and second input data.
19. 19 . The semiconductor system of claim 18 , wherein the data input circuit comprises: a first internal transmitter configured to drive the first input and output line to the first logic level when the precharge signal is enabled and configured to generate the first input data by driving the first input and output line to the second logic level when the first alignment data has the second logic level in synchronization with the internal strobe signal; and a second internal transmitter configured to drive the second input and output line to the first logic level when the precharge signal is enabled and configured to generate the second input data by driving the second input and output line to the second logic level when the second alignment data has the second logic level in synchronization with the internal strobe signal.
20. 20 . The semiconductor system of claim 18 , wherein the data output circuit comprises: a first internal receiver configured to generate the first internal data by driving a first node based on a logic level of the first input data; and a second internal receiver configured to generate the second internal data by driving a second node based on a logic level of the second input data.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2023-0077071, filed in the Korean Intellectual Property Office on Jun. 15, 2023, the entire disclosure of which is incorporated herein by reference. BACKGROUND The present disclosure relates to a semiconductor system for inputting and outputting data through multiple lines. In general, a semiconductor device including double data rate synchronous DRAM (DDR SDRAM) performs a read operation and write operation on data in response to a command that is input from an external chipset. The semiconductor device inputs and outputs data by using multiple input and output lines to perform the read operation and the write operation. As a process of manufacturing the semiconductor device becomes fine, an interval between the multiple input and output lines is implemented very narrowly. As the interval between multiple input and output lines becomes very narrow, an interference phenomenon between the input and output lines occurs. An error in which the logic level of data is not transitioned or the transition of the logic level of data becomes slow when intervals of time at which two input and output lines that are adjacent to each other are toggled are the same may occur. Various methods for preventing such an error of the level transition of data are required. SUMMARY In an embodiment, a data input and output circuit may include: a data input circuit configured to precharge first and second input and output lines after the end of a power-up operation and configured to generate first and second input data by driving the first and second input and output lines from each of which transfer data having a set logic level, among first and second transfer data, are output after the start of a write operation; and a data output circuit configured to generate first and second internal data based on logic levels of the first and second input data. In an embodiment, a semiconductor system may include: a controller configured to drive first and second transmission lines to a first logic level after the start of an initialization operation and configured to output first and second data by driving the first and second transmission lines from each of which pre-data having a second logic level, among first and second pre-data, are output after the start of a write operation; and a semiconductor device configured to drive first and second input and output lines to the first logic level after the end of a power-up operation, configured to generate first and second internal data by driving the first and second input and output lines from each of which transfer data having the second logic level, among first and second transfer data that are generated from the first and second data, are output after the start of the write operation, and configured to store the first and second internal data. In an embodiment, a semiconductor system may include: a controller configured to output a clock and a command address and configured to output first and second data in series; and a semiconductor device configured to drive first and second input and output lines to a first logic level after the end of a power-up operation, configured to generate first and second alignment data by parallelizing first and second data based on the command address after the start of a write operation, configured to generate first and second internal data by driving the first and second input and output lines from each of which alignment data having a second logic level, among the first and second alignment data, are output, and configured to store the first and second internal data. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a construction of a semiconductor system according to an embodiment of the present disclosure. FIG. 2 is a block diagram illustrating a construction according to an embodiment of a transmission circuit that is included in the semiconductor system illustrated in FIG. 1. FIG. 3 is a circuit diagram illustrating a construction according to an embodiment of a first transmitter that is included in the transmission circuit illustrated in FIG. 2. FIG. 4 is a circuit diagram illustrating a construction according to another embodiment of the first transmitter that is included in the transmission circuit illustrated in FIG. 2. FIG. 5 is a circuit diagram illustrating a construction according to still another embodiment of the first transmitter that is included in the transmission circuit illustrated in FIG. 2. FIG. 6 is a timing diagram for describing an operation of the first transmitter illustrated in FIG. 3. FIG. 7 is a timing diagram for describing an operation of the transmission circuit illustrated in FIG. 1. FIG. 8 is a block diagram illustrating a construction according to an embodiment of a semiconductor device that is included in the semiconductor system illustrated in FIG. 1. FIG. 9