US-12620436-B2 - Multi-ported memory array utilizing bitcells with balanced P-N diffusion layouts

Abstract

A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes first, second, and third sets of a plurality of transistor devices. The first set is configured to form at least one write port. The at least one write port receives digital data. The second set of the plurality of transistor devices is configured as an inverter pair that stores the digital data. The third set of the plurality of transistor devices is configured to form at least one read port. The at least one read port is used to access the digital data from the inverter pair and output the digital data on the local bitline. The plurality of transistor devices consists of an equal number of P-channel transistor devices and N-channel transistor devices.

Inventors

• Amlan Ghosh
• John R. Riley
• Feroze Merchant
• Jaydeep Kulkarni

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20220629

Claims (20)

1. 1 . A memory device comprising: at least one bitcell coupled to a local bitline, the local bitline comprising a plurality of pre-discharge devices, and the at least one bitcell comprising: a first set of a plurality of transistor devices configured to form at least one write port, the at least one write port to receive digital data; a second set of the plurality of transistor devices configured as an inverter pair, the inverter pair to store the digital data; a third set of the plurality of transistor devices configured to form at least one read port, the at least one read port to access the digital data stored at the inverter pair and output the digital data to a node on the local bitline, and the plurality of transistor devices consisting of an equal number of P-channel transistor devices and N-channel transistor devices, wherein the first set and the third set comprise transistor devices of a different type, at least one of the first set or the third set comprises transistor devices with a common gate terminal, and at least one of the plurality of pre-discharge devices pre-discharges the node to a source supply voltage (Vss); and read merge circuitry coupled to the local bitline, the read merge circuitry comprising a plurality of pre-discharge devices coupled to a corresponding plurality of clipper devices, and the read merge circuitry to: pre-discharge a node of the local bitline at a first read port of the at least one read port of the bitcell to a source supply voltage (Vss) at a first pre-discharge device of the plurality of pre-discharge devices; initiate charge sharing between the node of the local bitline and a full swing local bitline node of the read merge circuitry via a first clipper device of the plurality of clipper devices; and assert a read wordline (RWL) at a read transfer transistor of the bitcell to cause a read operation at the first read port.
2. 2 . The memory device of claim 1 , wherein the plurality of transistor devices consists of four N-channel metal-oxide semiconductor (NMOS) transistors and four P-channel metal-oxide semiconductor (PMOS) transistors.
3. 3 . The memory device of claim 2 , wherein the at least one write port is a single write (1 W) port formed by two PMOS transistors of the four PMOS transistors, the two PMOS transistors having the common gate terminal.
4. 4 . The memory device of claim 3 , wherein the at least one read port comprises two read (2R) ports formed by two of the four NMOS transistors.
5. 5 . The memory device of claim 1 , wherein the P-channel transistor devices and the N-channel transistor devices comprise complementary field-effect transistors (CFETs).
6. 6 . The memory device of claim 1 , wherein the at least one read port is a single read (1R) port formed by at least two of the N-channel transistor devices, the at least one read port configured for a differential read of the digital data stored in the inverter pair.
7. 7 . The memory device of claim 1 , wherein the at least one write port is formed by two of the P-channel transistor devices.
8. 8 . The memory device of claim 7 , wherein gate terminals of the two of the P-channel transistor devices form a write-wordline-bar (wwl_b) terminal associated with writing the digital data into the inverter pair.
9. 9 . The memory device of claim 1 , wherein the at least one bitcell is configured as one of: an eight-transistor (8T) two read port and one write port (2R1W) bitcell; an 8T one read port and one write port (1R1W) bitcell, wherein the one read port is configured for a single-ended read operation; and an 8T 1R1W bitcell, wherein the one read port is configured for a differential read operation.
10. 10 . A memory device comprising: a plurality of bitcells coupled via a local bitline, each bitcell of the plurality of bitcells comprising at least two read ports; and read merge circuitry coupled to the local bitline, the read merge circuitry comprising a plurality of pre-discharge devices coupled to a corresponding plurality of clipper devices, and the read merge circuitry to: pre-discharge a node of the local bitline at a first read port of the at least two read ports of the bitcell to a source supply voltage (Vss) at a first pre-discharge device of the plurality of pre-discharge devices; initiate charge sharing between the node of the local bitline and a full swing local bitline node of the read merge circuitry via a first clipper device of the plurality of clipper devices; and assert a read wordline (RWL) at a read transfer transistor of the bitcell to cause a read operation at the first read port.
11. 11 . The memory device of claim 10 , wherein the read merge circuitry further comprises: a first N-channel metal-oxide semiconductor (NMOS) transistor configured as the first pre-discharge device.
12. 12 . The memory device of claim 11 , wherein the first pre-discharge device is configured to pre-discharge the node of the local bitline based on a clock select high voltage signal asserted at a gate of the first NMOS transistor.
13. 13 . The memory device of claim 11 , wherein the read merge circuitry further comprises: a P-channel metal-oxide semiconductor (PMOS) transistor configured as a pre-charge device.
14. 14 . The memory device of claim 13 , wherein the pre-charge device is configured to charge the full swing local bitline node of the read merge circuitry before the charge sharing, based on a clock select low voltage signal asserted at a gate of the PMOS transistor.
15. 15 . The memory device of claim 13 , wherein the read merge circuitry further comprises: a second NMOS transistor configured as the first clipper device.
16. 16 . The memory device of claim 15 , wherein the first clipper device is configured to initiate the charge sharing between the node of the local bitline and the full swing local bitline node of the read merge circuitry based on a clock select high voltage signal asserted at a gate of the second NMOS transistor.
17. 17 . A method for performing a memory access operation, the method comprising: pre-discharging at a pre-discharge device of a plurality of pre-discharge devices coupled to a corresponding plurality of clipper devices, a node of a local bitline at a first read port of at least two read ports of a bitcell to a source supply voltage (Vss); initiating a charge sharing between a node of the local bitline and a full swing local bitline node of a read merge circuitry coupled to the local bitline; and asserting a read wordline (RWL) at a read transfer transistor of the bitcell to cause a read operation at the first read port.
18. 18 . The method of claim 17 , further comprising: asserting a first clock select high voltage signal at a gate of a first N-channel metal-oxide semiconductor (NMOS) transistor of the read merge circuitry to perform the pre-discharging of the node of the local bitline.
19. 19 . The method of claim 18 , further comprising: assert a clock select low voltage signal at a gate of a P-channel metal-oxide semiconductor (PMOS) transistor of the read merge circuitry to charge the full swing local bitline node of the read merge circuitry before the charge sharing.
20. 20 . The method of claim 19 , further comprising: asserting a second clock select high voltage signal at a gate of a second NMOS transistor of the read merge circuitry to initiate the charge sharing between the node of the local bitline and the full swing local bitline node of the read merge circuitry.

Description

TECHNICAL FIELD Embodiments pertain to improvements in memory architectures, including techniques for high-density multi-ported low-swing memory arrays utilizing one or more bitcells (e.g., one or more eight-transistor (8T) bitcells) having balanced, fully populated P-N type semiconductor diffusion layouts. BACKGROUND With the increased use of memory devices, further performance improvements in processing efficiency and implementation footprint are relevant considerations. Conventional memory arrays are typically associated with layout transition region spacing and reduced utilization of the available diffusion space, which increases the implementation footprint and reduces area efficiency. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings, like numerals may describe the same or similar components or features in different views. Like numerals having different letter suffixes may represent different instances of similar components. Some embodiments are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which: FIG. 1 is a block diagram of a radio architecture including an interface card with a memory device configured according to disclosed techniques, in accordance with some embodiments; FIG. 2 illustrates a front-end module circuitry for use in the radio architecture of FIG. 1, in accordance with some embodiments; FIG. 3 illustrates a radio IC circuitry for use in the radio architecture of FIG. 1, in accordance with some embodiments; FIG. 4 illustrates a baseband processing circuitry for use in the radio architecture of FIG. 1, in accordance with some embodiments; FIG. 5 illustrates a balanced P-N 8T bitcell configured as a two-read-ports-one-write-port (2R1 W) bitcell with PMOS transistors used at the write terminals, in accordance with some embodiments; FIG. 6 illustrates a balanced P-N 8T bitcell configured as a 1R1 W bitcell with a single-ended read, in accordance with some embodiments; FIG. 7 illustrates a balanced P-N 8T bitcell configured as a 1R1 W bitcell with a differential read, in accordance with some embodiments; FIG. 8 illustrates a balanced P-N 8T bitcell configured as a 2R1 W bitcell with NMOS transistors used at the write terminals, in accordance with some embodiments; FIG. 9 illustrates a memory device configured with multiple bitcells and a read merge circuit performing a read operation, in accordance with some embodiments; FIG. 10 illustrates a graphical representation of signals used by the memory device of FIG. 9, in accordance with some embodiments; FIG. 11 illustrates cross-coupled and pull-down PMOS in a read merge circuit for area reduction, in accordance with some embodiments; FIG. 12 illustrates a flow diagram of a method for performing a memory access operation, in accordance with some embodiments; and FIG. 13 illustrates a block diagram of an example machine upon which any one or more of the operations/techniques (e.g., methodologies) discussed herein may perform. DETAILED DESCRIPTION The following detailed description refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc., to provide a thorough understanding of the various aspects of various embodiments. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the various embodiments may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the various embodiments with unnecessary detail. The following description and the drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in or substituted for, those of other embodiments. Embodiments outlined in the claims encompass all available equivalents of those claims. The disclosed techniques can be used to configure memory devices to address the following technical deficiencies of existing memory device technologies: (a) Bitcell area: utilize 100% of the available diffusion space for active transistors to minimize the bitcell area; (b) Scalability: develop a scalable bitcell topology with an equal number of P/N which can effectively leverage future Complementary FET (CFET) technology (with P device implemented on top of an NFET or vice versa) for aggressive area scaling; (c) Array efficiency: eliminate the transition region layout spacing typically used between the peripheral standard logic cells and custom 8T 1R1 W Static Random Access Memory (SRAM) b