US-12620437-B2 - Memory device, assist cell and double assist cell for a memory device

Abstract

A memory device comprising at least one memory bank is provided and comprises a two-dimensional array of memory cells, a plurality of local bit lines connecting all memory cells in a first dimension of the two-dimensional array, a plurality of word lines connecting all memory cells in a second dimension of the two-dimensional array. The memory device further comprises at least one array of assist cells per memory bank, each array having one shared sense line and being arranged along memory cells and connected to by a bit line. The assist cells are configured as modified memory cells with a common sense line to provide a sense amplifier functionality. An assist cell and a double assist cell for a memory device are also provided.

Inventors

• Wolfgang Penth
• Jan Niklas Stegmaier
• Rolf Sautter
• Silke Penth

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260505

Application Date

20240108

Priority Date

20231004

Claims (19)

1. 1 . A memory device, comprising: at least one memory bank, including a two-dimensional array of memory cells; a plurality of local bit lines connecting all memory cells in a first dimension of the two-dimensional array; a plurality of word lines connecting all memory cells in a second dimension of the two-dimensional array; at least one array of assist cells per memory bank, each array having one shared sense line and being arranged along memory cells and connected to by a bit line; and wherein the assist cells are configured as modified memory cells with a common sense line to provide a sense amplifier functionality, and wherein in the assist cells two of at least six transistors of an assist memory cell that connect inner nodes of the memory cell with the local bit lines are short-circuited, in particular, are short-circuited via a wire connection of source and drain electrodes of the transistors.
2. 2 . The memory device according to claim 1 , wherein the memory cells are static random access memory cells.
3. 3 . The memory device according to claim 1 , wherein in assist cell gates of two of at least six transistors of the memory cell that connect the inner nodes of the memory cell with the local bit lines are connected to a power line.
4. 4 . The memory device according to claim 1 , wherein a ground connection of a memory cell is replaced by the common sense line which can be controlled from outside of the memory bank to enable or disable the assist cell.
5. 5 . The memory device according to claim 1 , further comprising a memory cell access circuitry, providing at least one multiplexer for the at least one memory bank per the first dimension associated with at least one local bit line of the at least one memory bank.
6. 6 . The memory device according to claim 5 , wherein the at least one multiplexer transfers the local bit lines to global bit lines for output.
7. 7 . The memory device according to claim 6 , wherein the transfer of the local bit lines to the global bit lines is driven by a local read enable line.
8. 8 . The memory device according to claim 1 , wherein an input/output device is provided comprising output drivers for transferring global bit lines to output lines.
9. 9 . The memory device according to claim 1 , wherein two memory banks are arranged in a double memory bank.
10. 10 . The memory device according to claim 9 , further comprising a memory cell access circuitry, providing at least one multiplexer for the double memory bank per the first dimension associated with at least one local bit line of each of two neighboring memory banks in the double memory bank.
11. 11 . The memory device according to claim 10 , wherein the at least one multiplexer transfers the local bit lines to global bit lines for output, in particular wherein the transfer of the local bit lines is driven by a local read enable line.
12. 12 . The memory device according to claim 9 , wherein an input/output device is provided comprising output drivers for transferring global bit lines to output lines.
13. 13 . The memory device according to claim 1 , wherein the assist cells in the array of assist cells are arranged pairwise as double assist cells.
14. 14 . An assist cell for a memory device, being configured as a modified memory cell of the memory device with a common sense line to provide a sense amplifier functionality, wherein in the assist cell two of at least six transistors of a memory cell that connect inner nodes of the memory cell with local bit lines are short-circuited, in particular, are short-circuited via a wire connection of source and drain electrodes of the transistors.
15. 15 . The assist cell according to claim 14 , wherein in the assist cell two of at least six transistors of a memory cell, that connect the inner nodes of the memory cell with the local bit lines, are short-circuited via a wire connection of the source and drain electrodes of the transistors: wherein a ground connection of the memory cell is replaced by the common sense line, which can be controlled from outside of a memory bank, to enable or disable the assist cell.
16. 16 . The assist cell according to claim 14 , wherein in assist cell gates of two of at least six transistors of the memory cell, that connect inner nodes of the assist cell with the local bit lines, are connected to a power line: wherein a ground connection of the memory cell is replaced by a common sense line, which can be controlled from outside of a memory bank, to enable or disable the assist cell.
17. 17 . A double assist cell for a memory device, being configured as two modified memory cells of the memory device with a common sense line to provide a function of a sense amplifier; and wherein in the double assist cell two of at least six transistors of a memory cell that connect inner nodes of the memory cell with local bit lines are short-circuited, in particular, are short-circuited via a wire connection of source and drain electrodes of the transistors.
18. 18 . The double assist cell according to claim 17 , wherein in the double assist cell two of at least six transistors of a single memory cell that connect inner nodes of the single memory cell with local bit lines are short-circuited via a wire connection of source and drain electrodes of the transistors: wherein a ground connection of the two memory cells is replaced by the common sense line which can be controlled from outside of a memory bank, to enable or disable the double assist cell.
19. 19 . The double assist cell according to claim 17 , wherein in double assist cell gates of two of at least six transistors of a single memory cell that connect inner nodes of the single memory cell with local bit lines are connected to a power line: wherein a ground connection of the two memory cells is replaced by a common sense line which can be controlled from outside of a memory bank, to enable or disable the double assist cell.

Description

The present invention relates in general to data processing systems, in particular, to a memory device. The invention further relates to an assist cell and a double assist cell for a memory device. BACKGROUND High performance memories in high performance microprocessors usually comprise static random-access memory (SRAM) cells. An SRAM cell is a type of semiconductor memory cell that has low power consumption and fast access time relative to a dynamic random-access memory (DRAM) cell. An SRAM cell comprises a latch and one or more access devices. A latch is a data storage unit in a semiconductor device comprising of two inverters. An inverter has an input and an output having a voltage of opposite polarity to said input. The inverter is connected between a system power voltage level and system ground voltage level. The latch stores binary data, and the access device provides the capability to read and write data into the latch. In a conventional single-port architecture, each bit in an SRAM cell is stored on four transistors that form two cross-coupled inverters operative as a storage element of the memory cell. Two additional transistors serve to control access to the storage element during read and write operations. A typical SRAM cell uses six transistors. High performance memories usually comprise array of memory cells, built of six transistor SRAM cells. A cell column can be selected by activating one of the word lines. The cells connected to the chosen word line can be read or written through the connected bit lines. There are two industry standard ways to read out an array of memory cells, the so-called ripple domino and the sense amplifier approach. In each case, the cell is driving the bit line connected to it or gets written by the same lines. If an SRAM cell is not able to fully discharge the large capacitance of the bit line within a cycle the sense amplifier approach could be chosen. In this case, the sense amplifier, however, will detect its value by sensing the voltage difference of a bit line true and a bit line complement. As all bit lines are occupied by a read or write action, it is not possible to read and write the array in the same cycle. The sense amplifier approach could as well be chosen when the cell is strong enough to discharge the capacitance in a single cycle. With the ripple domino approach array entities with a reduced number of word lines, so called banks, are used. The local read enables signals, a one hot bus, marks the bank to be read in the given cycle. The local evaluation circuit of the selected bank drives the global bit line to the read value, other local evaluation circuits stay electrically isolated from the global bit line. This scheme enables read and write in different banks of the same array in the same cycle. SUMMARY A memory device is proposed, comprising at least one memory bank, including a two-dimensional array of memory cells; a plurality of local bit lines connecting all memory cells in a first dimension of the two-dimensional array; a plurality of word lines connecting all memory cells in a second dimension of the two-dimensional array; at least one array of assist cells per memory bank, each array having one shared sense line and being arranged along memory cells and connected to by a bit line. The assist cells are configured as modified memory cells with a common sense line to provide a sense amplifier functionality. Advantageously, the read or write signal of a memory cell is amplified with a small, in particular, minimum, logical, area and power impact by using instances of the memory cell for the amplification. For instance, columns of the array may extend into the first dimension of the array and rows of the array may extend into the second dimension of the array, or vice versa. The proposed memory device overcomes disadvantages of actual technologies. Bit lines get fully discharged in each condition and thus the low voltage performance and even low voltage operation of an array is enhanced. Using assist cells is also advantageous as resistances of wires and vias have grown in relation to the device strength. The bistable circuit of the assist cells does not require the knowledge of the data value for the formation of the assist signal. Also, it enables the circuit to assist in a read action on top of the write assist. The additional assist cells speed up read and write actions. In the proposed memory device, the footprint and silicon of a standard memory cell is taken and with few metal changes is used as assist circuit for read and write processes of the memory device. This procedure can be combined with different assist voltages. In the memory device the bit line is amplified according to the memory strength, as it is built from memory cells and sitting right next to them, thus assisting for read and write processes. Limited space on the memory device may be needed to account for statistical device differences. Usage of modified memory cells ke