US-12620438-B2 - Retention mode low leakage high performance bit line clamping scheme based on an output latch state

Abstract

An on-chip static RAM (SRAM) is disclosed. In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows, a read bit line for each column of the array of memory cells, and an output latch to store a bit for one of the array of memory cells when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell in the column is connected to the read bit line for that column and the output latch includes a transistor that does not allow the read bit line for the column corresponding to the one of the array of memory cells to pre-charge when a data latch in the output latch is in a high state.

Inventors

• Lalit Gupta
• Cagri Erbagci

Assignees

• NVIDIA CORPORATION

Dates

Publication Date

20260505

Application Date

20240531

Claims (20)

1. 1 . An on-chip static RAM (SRAM), comprising: an array of memory cells arranged in columns and rows; a read bit line (RBL) and read bit line complement ( RBL ) for each column of the array of memory cells, wherein each memory cell in the column is connected to the RBL and RBL for that column; a word line (WL) for each row of the array of memory cells, wherein each memory cell in the row is connected to the WL of that row; an output latch to store a bit for one of the array of memory cells in a data latch of the output latch when the on-chip SRAM is in a retention mode, the output latch external to the one of the array of memory cells; and a first transistor of the output latch, wherein when the data latch is in a high state, the first transistor prevents pre-charging of the RBL for the column corresponding to the one of the array of memory cells when in the retention mode.
2. 2 . The on-chip static RAM (SRAM) as recited in claim 1 , wherein the output latch further comprises a second and third transistor controlled by a memory controller.
3. 3 . The on-chip static RAM (SRAM) as recited in claim 2 , wherein the second transistor is controlled by a read pre-charge signal (R PC ) received from the memory controller.
4. 4 . The on-chip static RAM (SRAM) as recited in claim 2 , wherein the third transistor is controlled by a read pre-charge keeper signal ( R PK ) received from the memory controller.
5. 5 . The on-chip static RAM (SRAM) as recited in claim 1 , wherein the output latch receives a retention enable signal (RET_EN) from a memory controller that indicates when the on-chip SRAM is entering or emerging from the retention mode.
6. 6 . The on-chip static RAM (SRAM) as recited in claim 5 , wherein the output latch includes a NOR gate and generates an output Q when the NOR gate receives the RET_EN and an output from the data latch.
7. 7 . A method of pre-charging a read bit line of an on-chip static RAM (SRAM) comprising an array of memory cells arranged in columns and rows, the method comprising: storing a bit for one of the array of memory cells in a data latch of an output latch external to the one of the array of memory cells when the on-chip SRAM enters a retention mode; and when the data latch is in a high state, allowing the read bit line to float rather than pre-charge when in the retention mode.
8. 8 . The method of pre-charging a read bit line as recited in claim 7 , wherein the read bit line is a read bit line complement ( RBL ).
9. 9 . The method of pre-charging a read bit line as recited in claim 7 , wherein a first transistor of the output latch allows the read bit line to float.
10. 10 . The method of pre-charging a read bit line as recited in claim 7 , further comprising controlling a second transistor of the output latch by a read pre-charge signal (R PC ) from a memory controller.
11. 11 . The method of pre-charging a read bit line as recited in claim 7 , further comprising controlling a third transistor by a read pre-charge keeper signal ( R PK ) from a memory controller.
12. 12 . The method of pre-charging a read bit line as recited in claim 7 , further comprising indicating when the on-chip SRAM is entering or emerging from the retention mode based on a retention enable signal (RET_EN) received by the output latch from a memory controller.
13. 13 . The method of pre-charging a read bit line as recited in claim 12 , further comprising generating an output Q from the output latch when the RET_EN signal and an output from the data latch is applied to a NOR gate of the output latch.
14. 14 . An integrated circuit (IC), comprising: a memory controller to generate a retention enable signal (RET_EN); and an on-chip static RAM (SRAM) including: an array of memory cells arranged in columns and rows; and an output latch to store a bit for one of the array of memory cells in a data latch of the output latch when the on-chip SRAM is in a retention mode,, the output latch external to the one of the array of memory cells, wherein the retention mode is based on the RET_EN signal and a first transistor of the output latch prevents pre-charging a read bit line complement ( RBL ) for a column of the array of memory cells corresponding to the one of the array of memory cells when in the retention mode and the data latch is in a high state.
15. 15 . The IC as recited in claim 14 , wherein the output latch further comprises a second and third transistor controlled by a memory controller.
16. 16 . The IC as recited in claim 15 , wherein the second transistor is controlled by a read pre-charge signal (R PC ) received from the memory controller.
17. 17 . The IC as recited in claim 15 , wherein the third transistor is controlled by a read pre-charge keeper signal ( R PK ) received from the memory controller.
18. 18 . The IC as recited in claim 14 , wherein the output latch receives a retention enable signal (RET_EN) from a memory controller that indicates when the on-chip SRAM is entering or emerging from the retention mode.
19. 19 . The IC as recited in claim 18 , wherein the output latch includes a NOR gate and generates an output Q when the NOR gate receives the RET_EN signal and an output from the data latch.
20. 20 . A library of circuit designs, comprising: a design for an on-chip static RAM (SRAM), wherein the SRAM includes: an array of memory cells arranged in columns and rows; a read bit line (RBL) and read bit line complement ( RBL ) for each column of the array of memory cells wherein each memory cell in the column is connected to the RBL and RBL for that column; a word line (WL) for each row of the array of memory cells wherein each memory cell in the row is connected to the WL of that row; an output latch to store a bit for one of the array of memory cells in a data latch of the output latch when the on-chip SRAM is in a retention mode, the output latch external to the one of the array of memory cells; and a first transistor of the output latch, wherein when the data latch is in a high state, the first transistor prevents pre-charging of the RBL for the column corresponding to the one of the array of memory cells when in the retention mode.

Description

TECHNICAL FIELD This application is directed, in general, to on-chip static RAMs (SRAMs) and, more specifically, to a low leakage, high performance bit line clamping scheme based on a state of an output latch in retention mode. BACKGROUND In large-scale integrated circuits (ICs), the consumption of power is of significant interest. Faster and faster speeds of these ICs mean higher and higher power consumption by the ICs. Moreover, operation of many circuits in these ICs, e.g., on-chip SRAMs, also add to higher power consumption because of leakage of current in, e.g., transistors at idle. In some applications of the ICs, for example battery powered applications such as mobile communication devices, management of the power consumed by the IC is important so that performance levels of the IC can continue to increase. SUMMARY OF THE DISCLOSURE In one aspect, an on-chip static RAM (SRAM) is disclosed. In one embodiment, the on-chip SRAM comprises an array of memory cells arranged in columns and rows, a read bit line (RBL) and read bit line complement (RBL) for each column of the array of memory cells, a word line (WL) for each row of the array of memory cells, and an output latch to store a bit for one of the array of memory cells in a data latch of the output latch when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell in the column is connected to the RBL and RBL for that column and each memory cell in the row is connected to the WL of that row. In one embodiment, the output latch includes a first transistor where when the data latch is in a high state, the first transistor prevents pre-charging of the (RBL) for the column corresponding to the one of the array of memory cells. In another aspect, a method of pre-charging a read bit line of an on-chip static RAM (SRAM) comprising an array of memory cells arranged in columns and rows is disclosed. In one embodiment, the method comprises storing a bit for one of the array of memory cells in a data latch of an output latch when the on-chip SRAM enters a retention mode and, when the data latch is in a high state, allowing the read bit line to float rather than pre-charge. In another aspect, an integrated circuit (IC) is disclosed. In one embodiment, the IC comprises a memory controller to generate a retention enable signal (RET_EN) and an on-chip static RAM (SRAM). In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows and an output latch to store a bit for one of the array of memory cells in a data latch of the output latch when the on-chip SRAM is in a retention mode. In one embodiment, the retention mode is based on the RET_EN signal and a first transistor of the output latch prevents pre-charging a read bit line complement (RBL) for a column of the array of memory cells corresponding to the one of the array of memory cells when the data latch is in a high state. In still another aspect, a library of circuit designs is disclosed. In one embodiment, the library comprises a design for an on-chip static RAM (SRAM). In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows, a read bit line (RBL) and read bit line complement (RBL) for each column of the array of memory cells, a word line (WL) for each row of the array of memory cells, and an output latch to store a bit for one of the array of memory cells in a data latch of the output latch when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell in the column is connected to the RBL and RBL for that column. In one embodiment, when the data latch is in a high state, a first transistor of the output latch prevents pre-charging of RBL for the column corresponding to the one of the array of memory cells. In yet another aspect, a battery powered mobile communications device comprising an integrated circuit (IC) is disclosed. In one embodiment, the IC comprises at least one processor, a memory controller, and an on-chip memory. In one embodiment, the on-chip memory includes an array of memory cells arranged in columns and rows, a read bit line (RBL) and read bit line complement (RBL) for each column of the array of memory cells, a word line (WL) for each row of the array of memory cells, and an output latch to store a bit for one of the array of memory cells in a data latch of the output latch when the on-chip memory is in a retention mode. In one embodiment, each memory cell in the column is connected to the RBL and RBL for that column and each memory cell in the row is connected to the WL of that row. In one embodiment, a first transistor of the output latch is controlled by the memory controller, where when the data latch is in a high state, the first transistor prevents pre-charging of the RBL for the column corresponding to the one of the array of memory cells. In still yet another aspect, an on-chip static memory is disclosed. In one embodiment, the on-chip memory includes an array