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US-12620439-B2 - Non-volatile memory device

US12620439B2US 12620439 B2US12620439 B2US 12620439B2US-12620439-B2

Abstract

A non-volatile memory device ( 1 ) includes a memory element ( 4 ) that can perform a program operation, a switch ( 9 ) having its first terminal connected to an application terminal for a first supply voltage (VDD), an even number of inverters ( 5, 6 ) of which input side is connected to a first node (N 1 ) to which the second terminal of the switch and the memory element are connected, and a current limiter ( 8 ) that limits the current flowing through the path via the application terminal for the first supply voltage, the transistor, and the memory element when a high-side transistor ( 61 ) included in the final-stage inverter ( 6 ) arranged in the final stage in the even number of inverters is on.

Inventors

  • Seiji Takenaka

Assignees

  • ROHM CO., LTD.

Dates

Publication Date
20260505
Application Date
20240730
Priority Date
20220202

Claims (6)

  1. 1 . A non-volatile memory device comprising: a memory element operable to perform a program operation; a switch having a first terminal connected to an application terminal for a first supply voltage; an even number of inverters of which an input side is connected to a first node to which a second terminal of the switch and the memory element are connected, and a current limiter configured to limit a current flowing through a path via the application terminal for the first supply voltage, the transistor, and the memory element, when a high-side transistor included in a final-stage inverter arranged in a final stage in the even number of inverters is on.
  2. 2 . A non-volatile memory device according to claim 1 , wherein the current limiter is a resistive element connected between an output terminal of the final-stage inverter and the first node.
  3. 3 . A non-volatile memory device according to claim 1 , wherein the current limiter is an on resistance of the transistor, and the output terminal of the final-stage inverter and the first node are short-circuited together.
  4. 4 . A non-volatile memory device according to claim 2 , further comprising: a reference element configured to constitute a current mirror together with the memory element, and a first constant current source connected between an application terminal for a second supply voltage and the reference element, wherein the first supply voltage is a voltage lower than the second supply voltage.
  5. 5 . A non-volatile memory device according to claim 1 , wherein the current limiter is a second constant current source connected between the application terminal for the first supply voltage and the transistor, and the output terminal of the final-stage inverter and the first node are short-circuited together.
  6. 6 . A non-volatile memory device according to claim 1 , further comprising: a reference element configured to constitute a current mirror together with the memory element, and a first constant current source connected between an application terminal for a second supply voltage and the reference element, wherein the first constant current source is switchable between an enabled state and a disabled state according to an enable signal, and the switch is switchable between on and off according to a reset signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This nonprovisional application is a continuation application of International Patent Application No. PCT/JP2023/003014 filed on Jan. 31, 2023, which claims priority Japanese Patent Application No. 2022-014738 filed on Feb. 2, 2022, the entire contents of which are hereby incorporated by reference. TECHNICAL FIELD The present disclosure relates to a non-volatile memory device. BACKGROUND ART Some known non-volatile memory devices employ hot carrier injection into transistors. This kind of non-volatile memory device includes as memory elements a first and a second transistor that have paired characteristics in their initial state and the characteristics of one of the transistors are changed by hot carrier injection. After that, in a read operation, based on the magnitude relationship between the drain currents of the first and second transistors as observed when a common gate voltage is fed to them, whether data “0” or data “1” is stored is read out. For example, a state where the drain current of the first transistor is lower (a state where the characteristics of the first transistor have been changed) corresponds to a state where data “0” is stored, and a state where the drain current of the second transistor is lower (a state where the characteristics of the second transistor have been changed) corresponds to a state where data “1” is stored. An example of technology related to what has just been mentioned is disclosed in Patent Document 1. CITATION LIST Patent Literature Patent Document 1: Japanese Unexamined Patent Application Publication No. 2011-103158 BRIEF DESCRIPTION OF DRAWINGS FIG. 1A is a diagram showing the configuration of a non-volatile memory device according to a first embodiment. FIG. 1B is a diagram showing a configuration example of an inverter in the first embodiment. FIG. 2 is a diagram showing the gate-source voltage dependence of the drain current of a data element. FIG. 3 is a diagram showing a state, during a read operation, of the non-volatile memory device according to the first embodiment (with a data element before a program operation). FIG. 4 is a diagram showing a state, after the read operation, of the non-volatile memory device according to the first embodiment (with the data element before the program operation). FIG. 5 is a diagram showing a state, after the read operation, of the non-volatile memory device according to the first embodiment (with the data element after the program operation). FIG. 6 is a diagram showing the configuration of a non-volatile memory device according to a second embodiment. FIG. 7 is a diagram showing a configuration example of a constant current source in the second embodiment. FIG. 8 is a diagram showing the configuration of a non-volatile memory device according to a third embodiment. DESCRIPTION OF EMBODIMENTS Hereinafter, an illustrative embodiment will be described with reference to the drawings. Any of the non-volatile memory devices described below can be configured as a semiconductor integrated circuit. 1. First Embodiment FIG. 1A is a diagram showing the configuration of a non-volatile memory device 1 according to a first embodiment. The non-volatile memory device 1 shown in FIG. 1A includes a constant current source 2, a reference element 3, a data element 4, inverters 5 to 7, a resistive element 8, and a switch 9. The reference element 3 and the data element 4 are both configured as memory elements and are configured, more specifically, as NMOS transistors (N-channel MOSFET (metal-oxide-semiconductor field-effect transistors)). A memory element is an element that can perform a program operation by changing the characteristics of a transistor by hot carrier injection, and is also called an OTP (one-time programmable) element. The data element 4 is the target for which the program operations is performed. The gate and the drain of the reference element 3 are short-circuited together. The constant current source 2 is connected between the drain of the reference element 3 and an application terminal for a supply voltage VCC. The source of the reference terminal 3 is connected to a ground terminal (an application terminal for a ground potential). The gate of the data element 4 is connected to the gate of the reference element 3. The source of the data element 4 is connected to the ground terminal. Thus, the reference element 3 and the data element 4 constitute a current mirror. One terminal of the switch 9 is connected to an application terminal for the supply voltage VDD. The other terminal of the switch 9 is connected to the drain of the data element 4 at a node N1. The node N1 is connected to the input terminal of the inverter 5. The input terminal of the inverter 6 is connected to the output terminal of the inverter 5. The output terminal of the inverter 6 is connected to the input terminal of the inverter 7 at a node N2. The node N2 is connected to one terminal of the resistive element 8. The