US-12620441-B2 - Memory, operation method of memory, and memory system

US12620441B2US 12620441 B2US12620441 B2US 12620441B2US-12620441-B2

Abstract

A memory includes a memory array and a peripheral circuit, wherein the memory array includes memory cells; the memory cells include a plurality of first memory cells coupled with a first selected word line, and a plurality of second memory cells coupled with a second selected word line; and the peripheral circuit is configured to: acquire a grouping result of the plurality of second memory cells, and if a first memory cell is coupled with a second memory cell in a first group through a first bit line, apply a first read voltage to the first memory cell at a first read duration; and if a first memory cell is coupled with a second memory cell in a second group through a second bit line, apply a second read voltage to the first memory cell at a second read duration.

Inventors

XiangNan Zhao
Songmin Jiang
Tingze WANG
Chenhui Li

Assignees

YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20240621
Priority Date: 20240417

Claims (20)

1 . A memory, comprising: a memory array comprising: memory cells comprising: a plurality of first memory cells coupled with a first selected word line, and a plurality of second memory cells coupled with a second selected word line, wherein the first selected word line and the second selected word line are adjacent to each other in terms of word line distribution structure; and a peripheral circuit configured to: after performing a program operation on the plurality of second memory cells coupled with the second selected word line, acquire a grouping result of the plurality of second memory cells, wherein the grouping result comprises a first group and a second group, the program operation comprises a first program stage and a second program stage, and voltage differences of the second memory cells in the first group in the first program stage and the second program stage are less than voltage differences of the second memory cells in the second group in the first program stage and the second program stage; if a first memory cell is coupled with a second memory cell in the first group through a first bit line, apply a first read voltage to the first memory cell at a first read duration; and if a first memory cell is coupled with a second memory cell in the second group through a second bit line, apply a second read voltage to the first memory cell at a second read duration.
2 . The memory of claim 1 , wherein the peripheral circuit is further configured to: determine a grouping rule of the plurality of second memory cells based on a program mode of the plurality of second memory cells, wherein the grouping rule comprises groups corresponding to an erased state and programmed states; and group the plurality of second memory cells based on the grouping rule and the erased state or programmed states corresponding respectively to the plurality of second memory cells after the program operation, so as to obtain the grouping result.
3 . The memory of claim 2 , wherein the peripheral circuit is further configured to: after performing the program operation on the plurality of second memory cells coupled with the second selected word line, read the erased state or programmed states corresponding respectively to the plurality of second memory cells; and group the plurality of second memory cells based on the erased state or programmed states corresponding respectively to the plurality of second memory cells and based on the groups corresponding to the erased state and each programmed state in the grouping rule, so as to obtain the grouping result.
4 . The memory of claim 1 , wherein the peripheral circuit is further configured to: after performing the program operation on the plurality of second memory cells coupled with the second selected word line, read the voltage differences of the plurality of second memory cells in the first program stage and the second program stage; and group the plurality of second memory cells based on the voltage differences corresponding respectively to the plurality of second memory cells, so as to obtain the grouping result.
5 . The memory of claim 4 , wherein the peripheral circuit is further configured to: when the voltage difference of a second memory cell in the first program stage and the second program stage is less than a voltage difference threshold, determine that the second memory cell belongs to the first group; or when the voltage difference of a second memory cell in the first program stage and the second program stage reaches the voltage difference threshold, determine that the second memory cell belongs to the second group.
6 . The memory of claim 1 , wherein the first read duration is shorter than the second read duration, and the first read voltage and the second read voltage are the same; or the first read duration and the second read duration are the same; the first read voltage is a voltage that is obtained by performing a first offset operation between a reference voltage and a first offset voltage; the second read voltage is a voltage that is obtained by performing a second offset operation between the reference voltage and a second offset voltage; and the first read voltage is less than the second read voltage.
7 . The memory of claim 1 , wherein the peripheral circuit is further configured to: in the first program stage, perform a first program operation on the plurality of first memory cells coupled with the first selected word line to obtain n programmed states; in the first program stage, perform the first program operation on the plurality of second memory cells coupled with the second selected word line to obtain n programmed states; in the second program stage, perform a second program operation on the plurality of first memory cells coupled with the first selected word line to obtain m programmed states, wherein n and m are positive integers, and n≤m; and in the second program stage, perform the second program operation on the plurality of second memory cells coupled with the second selected word line to obtain m programmed states.
8 . The memory of claim 1 , wherein the peripheral circuit is further configured to: store the grouping result of the plurality of second memory cells to a latch; and if a first memory cell is coupled with a second memory cell through the first bit line, acquire, from the latch, a group to which the second memory cell belongs.
9 . An operation method of a memory, wherein the memory comprises a plurality of first memory cells coupled with a first selected word line, and a plurality of second memory cells coupled with a second selected word line, wherein the first selected word line and the second selected word line are adjacent to each other in terms of word line distribution structure; and the method comprises: after performing a program operation on the plurality of second memory cells, acquiring a grouping result of the plurality of second memory cells, wherein the grouping result comprises a first group and a second group, the program operation comprises a first program stage and a second program stage, and voltage differences of the second memory cells in the first group in the first program stage and the second program stage are less than voltage differences of the second memory cells in the second group in the first program stage and the second program stage; and if a first memory cell is coupled with a second memory cell in the first group through a first bit line, applying a first read voltage to the first memory cell at a first read duration; or if a first memory cell is coupled with a second memory cell in the second group through a second bit line, applying a second read voltage to the first memory cell at a second read duration.
10 . The method of claim 9 , wherein the acquiring the grouping result of the plurality of second memory cells comprises: determining a grouping rule of the plurality of second memory cells based on a program mode of the plurality of second memory cells, wherein the grouping rule comprises groups corresponding to an erased state and programmed states; and grouping the plurality of second memory cells based on the grouping rule and the erased state or programmed states corresponding respectively to the plurality of second memory cells after the program operation, so as to obtain the grouping result.
11 . The method of claim 10 , wherein the grouping the plurality of second memory cells based on the grouping rule and the erased state or programmed states corresponding respectively to the plurality of second memory cells after the program operation, so as to obtain the grouping result comprises: after performing the program operation on the plurality of second memory cells coupled with the second selected word line, reading the erased state or programmed states corresponding respectively to the plurality of second memory cells; and grouping the plurality of second memory cells based on the erased state or programmed states corresponding respectively to the plurality of second memory cells and based on the groups corresponding to the erased state and each programmed state in the grouping rule, so as to obtain the grouping result.
12 . The method of claim 9 , wherein the acquiring the grouping result of the plurality of second memory cells comprises: after performing the program operation on the plurality of second memory cells coupled with the second selected word line, reading the voltage differences of the plurality of second memory cells in the first program stage and the second program stage; and grouping the plurality of second memory cells based on the voltage differences corresponding respectively to the plurality of second memory cells, so as to obtain the grouping result.
13 . The method of claim 12 , wherein the grouping the plurality of second memory cells based on the voltage differences corresponding respectively to the plurality of second memory cells, so as to obtain the grouping result comprises: when the voltage difference of a second memory cell in the first program stage and the second program stage is less than a voltage difference threshold, determining that the second memory cell belongs to the first group; or when the voltage difference of a second memory cell in the first program stage and the second program stage reaches the voltage difference threshold, determining that the second memory cell belongs to the second group.
14 . The method of claim 9 , wherein the first read duration is shorter than the second read duration, and the first read voltage and the second read voltage are the same; or the first read duration and the second read duration are the same; the first read voltage is a voltage that is obtained by performing a first offset operation between a reference voltage and a first offset voltage; and the second read voltage is a voltage that is obtained by performing a second offset operation between the reference voltage and a second offset voltage.
15 . The method of claim 9 , wherein the first program stage comprises a first program operation, and the second program stage comprises a second program operation; and the method further comprises: performing the first program operation on the plurality of first memory cells coupled with the first selected word line to obtain n programmed states; performing the first program operation on the plurality of second memory cells coupled with the second selected word line to obtain n programmed states; performing the second program operation on the plurality of first memory cells coupled with the first selected word line to obtain m programmed states, wherein n and m are positive integers, and n≤m; and performing the second program operation on the plurality of second memory cells coupled with the second selected word line to obtain m programmed states.
16 . The method of claim 9 , further comprising: storing the grouping result of the plurality of second memory cells to a latch; and if a first memory cell is coupled with a second memory cell through the first bit line, acquiring, from the latch, a group to which the second memory cell belongs.
17 . A memory system, comprising: one or more memories each comprising: a memory array comprising: memory cells comprising: a plurality of first memory cells coupled with a first selected word line, and a plurality of second memory cells coupled with a second selected word line, wherein the first selected word line and the second selected word line are adjacent to each other in terms of word line distribution structure; and a peripheral circuit configured to: after performing a program operation on the plurality of second memory cells coupled with the second selected word line, acquire a grouping result of the plurality of second memory cells, wherein the grouping result comprises a first group and a second group, the program operation comprises a first program stage and a second program stage, and voltage differences of the second memory cells in the first group in the first program stage and the second program stage are less than voltage differences of the second memory cells in the second group in the first program stage and the second program stage; if a first memory cell is coupled with a second memory cell in the first group through a first bit line, apply a first read voltage to the first memory cell at a first read duration; and if a first memory cell is coupled with a second memory cell in the second group through a second bit line, apply a second read voltage to the first memory cell at a second read duration; and a memory controller coupled to the memories and configured to control the memories.
18 . The memory system of claim 17 , wherein the peripheral circuit is further configured to: determine a grouping rule of the plurality of second memory cells based on a program mode of the plurality of second memory cells, wherein the grouping rule comprises groups corresponding to an erased state and programmed states; and group the plurality of second memory cells based on the grouping rule and the erased state or programmed states corresponding respectively to the plurality of second memory cells after the program operation, so as to obtain the grouping result.
19 . The memory system of claim 18 , wherein the peripheral circuit is further configured to: after performing the program operation on the plurality of second memory cells coupled with the second selected word line, read the erased state or programmed states corresponding respectively to the plurality of second memory cells; and group the plurality of second memory cells based on the erased state or programmed states corresponding respectively to the plurality of second memory cells and based on the groups corresponding to the erased state and each programmed state in the grouping rule, so as to obtain the grouping result.
20 . The memory system of claim 17 , wherein the peripheral circuit is further configured to: after performing the program operation on the plurality of second memory cells coupled with the second selected word line, read the voltage differences of the plurality of second memory cells in the first program stage and the second program stage; and group the plurality of second memory cells based on the voltage differences corresponding respectively to the plurality of second memory cells, so as to obtain the grouping result.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims priority to Chinese Patent Application No. 202410468938X, which was filed Apr. 17, 2024, is titled “MEMORY, MEMORY OPERATING METHOD AND STORAGE SYSTEM,” and is hereby incorporated herein by reference in its entirety. TECHNICAL FIELD The present application relates to the technical field of memories, and particularly to a memory, an operation method of a memory, and a memory system. BACKGROUND A 3-Dimension (3D) memory comprises a plurality of memory cells, and according to the volume of data that can be stored by the memory cells, the types of the memory cells can be classified into a Single-Level Cell (SLC), a Multi-Level Cell (MLC), a Trinary-Level Cell (TLC), and a Quad-Level Cell (QLC), etc. SUMMARY The present application provides a memory, an operation method of a memory, and a memory system. The technical solutions are as follows: One aspect provides a memory. The memory comprises a memory array and a peripheral circuit, wherein the memory array comprises memory cells; the memory cells comprise a plurality of first memory cells coupled with a first selected word line, and a plurality of second memory cells coupled with a second selected word line, wherein the first selected word line and the second selected word line are adjacent to each other in terms of word line distribution structure; and the peripheral circuit is configured to: after performing a program operation on the plurality of second memory cells coupled with the second selected word line, acquire a grouping result of the plurality of second memory cells, wherein the grouping result comprises a first group and a second group, the program operation comprises a first program stage and a second program stage, and voltage differences of the second memory cells in the first group in the first program stage and the second program stage are less than voltage differences of the second memory cells in the second group in the first program stage and the second program stage;if a first memory cell is coupled with a second memory cell in the first group through a first bit line, apply a first read voltage to the first memory cell at a first read duration; andif a first memory cell is coupled with a second memory cell in the second group through a second bit line, apply a second read voltage to the first memory cell at a second read duration. In some examples, the peripheral circuit is further configured to: determine a grouping rule of the plurality of second memory cells based on a program mode of the plurality of second memory cells, wherein the grouping rule comprises groups corresponding to an erased state and programmed states; andgroup the plurality of second memory cells based on the grouping rule and the erased state or programmed states corresponding respectively to the plurality of second memory cells after the program operation, so as to obtain the grouping result. In some examples, the peripheral circuit is further configured to: after performing the program operation on the plurality of second memory cells coupled with the second selected word line, read the erased state or programmed states corresponding respectively to the plurality of second memory cells; andgroup the plurality of second memory cells based on the erased state or programmed states corresponding respectively to the plurality of second memory cells and based on the groups corresponding to the erased state and each programmed state in the grouping rule, so as to obtain the grouping result. In some examples, the peripheral circuit is further configured to: after performing the program operation on the plurality of second memory cells coupled with the second selected word line, read the voltage differences of the plurality of second memory cells in the first program stage and the second program stage; andgroup the plurality of second memory cells based on the voltage differences corresponding respectively to the plurality of second memory cells, so as to obtain the grouping result. In some examples, the peripheral circuit is further configured to: when the voltage difference of a second memory cell in the first program stage and the second program stage is less than a voltage difference threshold, determine that the second memory cell belongs to the first group; orwhen the voltage difference of a second memory cell in the first program stage and the second program stage reaches the voltage difference threshold, determine that the second memory cell belongs to the second group. In some examples, the first read duration is shorter than the second read duration, and the first read voltage and the second read voltage are the same; or the first read duration and the second read duration are the same; the first read voltage is a voltage that is obtained by performing a first offset operation between a reference voltage and a first offset voltage; the second read voltage is a voltage that is obtained by perform