US-12620442-B2 - Managing program disturb in memory devices

Abstract

Example apparatus and methods for managing program disturb in flash memory are disclosed. In one example, a memory device can include a memory string including a first select gate transistor, a second select gate transistor, and memory cells positioned in between. A peripheral circuit is configured to apply, during a program operation of a first memory cell, a first voltage to the first select gate transistor. The first memory cell is coupled to a first word line closest to the first select gate transistor among word lines coupled to the memory cells. The peripheral circuit is further configured to apply, during a program operation of a second memory cell, a second voltage to the first select gate transistor. The second memory cell is coupled to a second word line farther from the first select gate transistor than the first word line. The second voltage is higher than the first voltage.

Inventors

• Zihao Deng

Assignees

• YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260505

Application Date

20240711

Priority Date

20240419

Claims (20)

1. 1 . A memory device, comprising: a memory array comprising a first memory string, wherein the first memory string comprises a first select gate transistor, a second select gate transistor, and memory cells positioned between the first select gate transistor and the second select gate transistor; and a peripheral circuit coupled to the memory array, wherein the peripheral circuit is configured to: apply, during a first program operation of a first memory cell of the memory cells, a first voltage to a select line coupled to the first select gate transistor, wherein the first memory cell is coupled to a first word line that is closest to the first select gate transistor among word lines coupled to the memory cells; and apply, during a second program operation of a second memory cell of the memory cells, a second voltage to the select line coupled to the first select gate transistor, wherein the second memory cell is coupled to a second word line that is farther from the first select gate transistor than the first word line, and wherein the second voltage is higher than the first voltage.
2. 2 . The memory device of claim 1 , wherein the peripheral circuit is further configured to: apply, during a third program operation of a third memory cell of the memory cells, a third voltage to the select line coupled to the first select gate transistor, wherein the third memory cell is coupled to a third word line that is closer to the first select gate transistor than the second word line, and wherein the third voltage is higher than or equal to the first voltage and lower than the second voltage.
3. 3 . The memory device of claim 2 , wherein the third word line is a second closest word line to the first select gate transistor after the first word line.
4. 4 . The memory device of claim 2 , wherein the peripheral circuit is further configured to: apply, during a fourth program operation of a fourth memory cell of the memory cells, the second voltage to the select line coupled to the first select gate transistor, wherein the fourth memory cell is coupled to a fourth word line that is different from the first word line and the third word line.
5. 5 . The memory device of claim 1 , wherein the peripheral circuit is further configured to: apply, during a first time period of the first program operation, a fourth voltage to the select line coupled to the first select gate transistor, wherein the fourth voltage is lower than the first voltage; and apply, during a second time period of the first program operation, the first voltage to the select line coupled to the first select gate transistor, wherein the second time period follows the first time period.
6. 6 . The memory device of claim 5 , wherein the second time period comprises a third time period, a fourth time period following the third time period, and a fifth time period following the fourth time period, and wherein the peripheral circuit is further configured to: apply, during the third time period, a fifth voltage to the first word line; apply, during the fourth time period, a program voltage to the first word line; and apply, during the fifth time period, a sixth voltage to the first word line, wherein the fifth voltage and the sixth voltage are higher than the first voltage and lower than the program voltage.
7. 7 . The memory device of claim 6 , wherein the peripheral circuit is further configured to: apply, during the second time period, a pass voltage to the second word line.
8. 8 . The memory device of claim 1 , wherein the peripheral circuit is configured to program a memory cell coupled to the first word line before programming a memory cell coupled to the second word line.
9. 9 . The memory device of claim 1 , wherein the peripheral circuit is configured to program a memory cell coupled to the first word line after programming a memory cell coupled to the second word line.
10. 10 . The memory device of claim 1 , wherein the peripheral circuit is further configured to: apply, during the first program operation, a seventh voltage to a bit line coupled to a second memory string of the memory array, wherein the seventh voltage is higher than or equal to a difference between the first voltage and a predetermined threshold voltage of a first select gate transistor in the second memory string.
11. 11 . The memory device of claim 1 , wherein the memory array comprise one or more decks of memory cells, wherein a first deck of the one or more decks of memory cells is adjacent to a second deck of the one or more decks of memory cells, wherein a word line coupled to a memory cell in the first deck that is closest to the second deck is a dummy word line, and wherein a word line coupled to a memory cell in the second deck that is closest to the first deck is a dummy word line.
12. 12 . A method for operating a memory device, wherein the method comprises: applying, during a first program operation of a first memory cell, a first voltage to a select line coupled to a first select gate transistor, wherein the memory device comprises a memory array, wherein the memory array comprises a memory string comprising the first select gate transistor, a second select gate transistor, and memory cells positioned between the first select gate transistor and the second select gate transistor, wherein a first word line coupled to the first memory cell of the memory cells is closest to the first select gate transistor among word lines coupled to the memory cells; and applying, during a second program operation of a second memory cell of the memory cells, a second voltage to the select line coupled to the first select gate transistor, wherein the second memory cell is coupled to a second word line farther from the first select gate transistor than the first word line, and wherein the second voltage is higher than the first voltage.
13. 13 . The method of claim 12 , further comprising: applying, during a third program operation of a third memory cell of the memory cells, a third voltage to the select line coupled to the first select gate transistor, wherein the third memory cell is coupled to a third word line that closer to the first select gate transistor than the second word line, and wherein the third voltage is higher than or equal to the first voltage and lower than the second voltage.
14. 14 . The method of claim 13 , wherein the third word line is a second closest word line to the first select gate transistor after the first word line.
15. 15 . The method of claim 13 , further comprising: applying, during a fourth program operation of a fourth memory cell of the memory cells, the second voltage to the select line coupled to the first select gate transistor, wherein the fourth memory cell is coupled to a fourth word line that is different from the first word line and the third word line.
16. 16 . The method of claim 12 , further comprising: applying, during a first time period of the first program operation, a fourth voltage to the select line coupled to the first select gate transistor, wherein the fourth voltage is lower than the first voltage; and applying, during a second time period of the first program operation, the first voltage to the select line coupled to the first select gate transistor, wherein the second time period follows the first time period.
17. 17 . The method of claim 16 , wherein the second time period comprises a third time period, a fourth time period following the third time period, and a fifth time period following the fourth time period, wherein the method further comprises: applying, during the third time period, a fifth voltage to the first word line; applying, during the fourth time period, a program voltage to the first word line; and applying, during the fifth time period, a sixth voltage to the first word line, wherein the fifth voltage and the sixth voltage are higher than the first voltage and lower than the program voltage.
18. 18 . The method of claim 17 , further comprising: applying, during the second time period, a pass voltage to the second word line.
19. 19 . The method of claim 12 , further comprising: applying, during the first program operation, a seventh voltage to a bit line coupled to a second memory string of the memory array, wherein the seventh voltage is higher than or equal to a difference between the first voltage and a predetermined threshold voltage of a first select gate transistor in the second memory string.
20. 20 . A memory system, comprising: a memory device, comprising: a memory cell array comprising a memory string, wherein the memory string comprises a first select gate transistor, a second select gate transistor, and memory cells positioned between the first select gate transistor and the second select gate transistor; and a peripheral circuit coupled to the memory cell array and configured to: apply, during a first program operation of a first memory cell of the memory cells, a first voltage to a select line coupled to the first select gate transistor, wherein the first memory cell is coupled to a first word line that is closest to the first select gate transistor among word lines coupled to the memory cells; and apply, during a second program operation of a second memory cell of the memory cells, a second voltage to the select line coupled to the first select gate transistor, wherein the second memory cell is coupled to a second word line that is farther from the first select gate transistor than the first word line, and wherein the second voltage is higher than the first voltage; and a controller coupled to the memory device and configured to control the memory device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. 202410479948.3, filed on Apr. 19, 2024, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD This present disclosure generally relates to the field of semiconductor technology, and more particularly, to systems and methods for managing program disturb in memory devices. BACKGROUND Flash memory is a low-cost, high-density, nonvolatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed by flash memory, for example, program (write) and erase operations, to change the threshold voltage of each memory cell to a respective level. For NAND flash memory, an erase operation can be performed at the block level, a program operation can be performed at the page level, and a read operation can be performed at the page level. SUMMARY The present disclosure involves memory devices, memory systems, and methods for managing program disturb in flash memory. In an example, a memory device can include a memory array and a peripheral circuit. The memory array can include a memory string including a first select gate transistor, a second select gate transistor, and memory cells positioned between the first select gate transistor and the second select gate transistor. The peripheral circuit is configured to apply, during a first program operation of a first memory cell, a first voltage to a select line coupled to the first select gate transistor. The first memory cell is coupled to a first word line that is closest to the first select gate transistor among word lines coupled to the memory cells. The peripheral circuit is further configured to apply, during a second program operation of a second memory cell, a second voltage to the select line coupled to the first select gate transistor. The second memory cell is coupled to a second word line that is farther from the first select gate transistor than the first word line. The second voltage is higher than the first voltage. While generally described as computer-implemented software embodied on tangible media that processes and transforms the respective data, some or all of the aspects may be computer-implemented methods or further included in respective systems or other devices for performing this described functionality. The details of these and other aspects and implementations of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 illustrates an example of a schematic diagram of a memory device including peripheral circuits, according to some aspects of the present disclosure. FIG. 2 illustrates an example of a schematic diagram of a memory cell array, according to some aspects of the present disclosure. FIG. 3 illustrates an example of a side view of cross-sections of a memory cell array including memory strings, according to some aspects of the present disclosure. FIG. 4 illustrates an example memory cell stack that includes multiple decks of memory cells, according to some aspects of the present disclosure. FIG. 5 illustrates some example peripheral circuits, according to some aspects of the present disclosure. FIG. 6A illustrates an example of voltages of components in a memory block during programming of the memory block, according to some aspects of the present disclosure. FIG. 6B illustrates another example of voltages of components in a memory block during programming of the memory block, according to some aspects of the present disclosure. FIG. 7A illustrates another example of voltages of components in a memory block during programming of the memory block, according to some aspects of the present disclosure. FIG. 7B illustrates another example of voltages of components in a memory block during programming of the memory block, according to some aspects of the present disclosure. FIG. 8A illustrates another example of voltages of components in a memory block during programming of the memory block, according to some aspects of the present disclosure. FIG. 8B illustrates another example of voltages of components in a memory block during programming of the memory block, according to some aspects of the present disclosure. FIG. 9 illustrates an example of a flow chart of a method for reducing program disturb in a memory device, according to some aspects of the present disclosure. FIG. 10 illustrates a block diagram of an example system having a memory device, according to some aspects of the present disclosure. FIG. 11A illustrates a diagram of a memory card having a memory device, according to some aspects of the present disclosure. FIG. 11B illustrates a diagram of a solid-state drive (SSD) having a memory device, accor