US-12620443-B2 - Semiconductor memory device with operation-specific pass voltages

US12620443B2US 12620443 B2US12620443 B2US 12620443B2US-12620443-B2

Abstract

According to one embodiment, a semiconductor memory device includes a first memory sub-block and a second memory sub-block arranged in a first direction and a control circuit. The first memory sub-block includes a first memory cell and a first word line connected to the first memory cell. The second memory sub-block includes a second memory cell and a second word line connected to the second memory cell. The control circuit executes a first and a second write operation on the first memory cell. In the first write operation, the control circuit applies a program voltage to the first word line and a first unselect write voltage to the second word line. In the second write operation, the program voltage is applied to the first word line and a second unselect write voltage is applied to the second word line.

Inventors

Yasuhiro Shiino
Kenrou KIKUCHI

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260505
Application Date: 20230808
Priority Date: 20220907

Claims (7)

1 . A semiconductor memory device, comprising: a first sub memory block; a second sub memory block arranged with the first sub memory block along a first direction; and a bit line on a first side of the first sub memory block that is opposite from the second sub memory block in the first direction; a source line on a second side of the second sub memory block that is opposite from the first sub memory block in the first direction; and a control circuit configured to control operations on the first sub memory block and the second sub memory block, wherein the first sub memory block includes: a first memory cell that is electrically connected to the bit line and the source line, and a first word line that is electrically connected to the first memory cell, the second sub memory block includes: a second memory cell that is electrically connected to the bit line and the source line, and a second word line that is electrically connected to the second memory cell, and the control circuit is configured to: determine whether the second sub memory block is in a written state or an erased state, execute a first erasing operation on the first memory cell when the second sub memory block is determined to be in the written state, and execute a second erasing operation on the first memory cell when the second sub memory block is determined to be in the erased state, in the first erasing operation, the control circuit applies an erasing voltage to one or both of the bit line and the source line, a select erasing voltage, which is lower than the erasing voltage, to the first word line, and a first unselect erasing voltage, which is lower than the erasing voltage but higher than the select erasing voltage, to the second word line, and in the second erasing operation, the control circuit applies the erasing voltage to one or both of the bit line and the source line, the select erasing voltage to the first word line, and a second unselect erasing voltage, which is lower than the first unselect erasing voltage, to the second word line.
2 . The semiconductor memory device according to claim 1 , wherein the second unselect erasing voltage is equal to the select erasing voltage.
3 . The semiconductor memory device according to claim 1 , wherein the control circuit is configured to: receive a command for an instruction of the first erasing operation to execute the first erasing operation, and receive a command for an instruction of the second erasing operation to execute the second erasing operation.
4 . The semiconductor memory device according to claim 1 , wherein the control circuit is configured to execute a read-before-erasing operation on the second memory cell before executing either of the first erasing operation or the second erasing operation, and the control circuit, in the read-before-erasing operation, applies a read voltage to the second word line and a first unselect read voltage, which is higher than the read voltage, to the first word line.
5 . The semiconductor memory device according to claim 1 , wherein the first sub memory block includes: a plurality of first conductive layers that are arranged in the first direction, a first semiconductor portion that extends in the first direction and that faces the plurality of first conductive layers, and a first charge storage between the plurality of first conductive layers and the first semiconductor portion, the second sub memory block includes: a plurality of second conductive layers that are arranged in the first direction, a second semiconductor portion that extends in the first direction in the plurality of second conductive layers, the second semiconductor portion being electrically connected to the first semiconductor portion, and a second charge storage film between the plurality of second conductive layers and the second semiconductor portion, one of the plurality of first conductive layers functions as the first word line, and one of the plurality of second conductive layers functions as the second word line.
6 . The semiconductor memory device according to claim 5 , further comprising: a semiconductor pillar that extends in the first direction, wherein the semiconductor pillar includes: the first semiconductor portion, the second semiconductor portion, and a third semiconductor portion that is between the first sub memory block and the second sub memory block and connected to the first semiconductor portion and the second semiconductor portion.
7 . The semiconductor memory device according to claim 6 , wherein, when a width of an end portion of the first semiconductor portion on a side of the third semiconductor portion in a second direction intersecting the first direction is defined as a first width, a width of an end portion of the second semiconductor portion on a side of the third semiconductor portion in the second direction is defined as a second width, and a width of the third semiconductor portion in the second direction is defined as a third width, the third width is larger than the first width and the second width.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-142343, filed Sep. 7, 2022, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor memory device. BACKGROUND A semiconductor memory device is known that includes a substrate, memory blocks aligned with the substrate in a first direction intersecting a surface of the substrate, and a control circuit that controls the memory blocks. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram illustrating a semiconductor memory device according to a first embodiment. FIG. 2 is a schematic side view illustrating a semiconductor memory device according to the first embodiment. FIG. 3 is a schematic plan view illustrating a semiconductor memory device according to the first embodiment. FIG. 4 is a schematic block diagram illustrating a semiconductor memory device according to the first embodiment. FIG. 5 is schematic a circuit diagram of a semiconductor memory device according to the first embodiment. FIG. 6 is a schematic perspective view illustrating aspects of a semiconductor memory device according to the first embodiment. FIG. 7 is a schematic plan view illustrating aspects of a semiconductor memory device according to the first embodiment. FIG. 8 is a schematic cross-sectional view illustrating aspects of the semiconductor memory device according to the first embodiment. FIG. 9 is a schematic cross-sectional view illustrating aspects of a semiconductor memory device according to the first embodiment. FIGS. 10A, 10B, and 10C relate to aspects of a threshold voltage of a memory cell MC in which 3-bit data is recorded. FIG. 11 is a timing chart illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 12 is a schematic cross-sectional view illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 13 is a flowchart illustrating an operation method of a semiconductor memory device according to the first embodiment. FIG. 14 is a timing chart illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 15 is a schematic cross-sectional view illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 16 is a flowchart illustrating an operation method of a semiconductor memory device according to the first embodiment. FIG. 17 is a timing chart illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 18 is a schematic cross-sectional view illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 19 is a schematic cross-sectional view illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 20 is a flowchart illustrating an operation method of a semiconductor memory device according to the first embodiment. FIG. 21 is a timing chart illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 22 is a schematic cross-sectional view illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 23 is a schematic cross-sectional view illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 24 is a schematic cross-sectional view illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIGS. 25A and 25B are schematic histograms illustrating aspects of a semiconductor memory device according to a comparative example. FIGS. 26A and 26B are schematic views illustrating aspects of an operation method of a semiconductor memory device according to the first embodiment. FIG. 27 is a flowchart illustrating Modification 1 of a semiconductor memory device according to the first embodiment. FIG. 28 is a flowchart illustrating Modification 2 of a semiconductor memory device according to the first embodiment. FIG. 29 is a flowchart illustrating Modification 3 of a semiconductor memory device according to the first embodiment. FIG. 30 is a schematic cross-sectional view illustrating aspects of Modification 3 of the semiconductor memory device according to the first embodiment. FIG. 31 is a flowchart illustrating a semiconductor memory device according to a second embodiment. FIG. 32 is a timing chart illustrating aspects of a semiconductor memory device according to the second embodiment. FIG. 33 is a schematic cross-sectional view illustrating aspects of a semiconductor memory device according to the second embodiment. FIG. 34 is a schematic cross-sectional view illustrating as